sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Backup if libera.chat and freenode fall over: irc.oftc.net
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sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<sorear> it's lasted two full calendar months and I'm more optimistic now
<sorear> removed the reference to the near-unused OFTC channel
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<xentrac> what, libera?
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<pierce> <sorear> "it's lasted two full calendar..." <- I didn't understand this either
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<sorear> pierce: libera.chat has survived all of june and july
<solrize> 2 hours left in july in my timezone
<solrize> 5 4 3 2 1 ...
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<pierce> sorear: oh I see, I see
<pierce> Off topic, but has anyone successfully got qemu running a RISC-V guest with 3d accelleration?
<solrize> seems on topic to me
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<solrize> https://www.sparkfun.com/products/18036 any idea what the square chip near the usb connector is?
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<pierce> <solrize> "seems on topic to me" <- Sorry, I meant off topic wrt the discussion at hand
<pierce> I think I have discovered the "problem"
<pierce> Qemu is out of date
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