sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<MoeIcenowy> smaeul: BTW will OpenSBI export SBI_TIMER on C906?
<MoeIcenowy> (As I am now investigating on my custom C906 SoC with LiteX, I think posting here is more appropriate now ;-)
<MoeIcenowy> weird, the LiteX timer seems to have only clockevent, no clocksource
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<conchuod> Alistair doesn't come here right?
<muurkha> not by that name
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<smaeul> MoeIcenowy: currently there's no timer driver on C906, since the CLINT is non-standard. looks like OpenSBI's behavior in that case is to still export the extension, but have it do nothing (this probably is not correct...)
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<another|> *sigh* anyone got a working patchset for v extensions for linux?
<conchuod> Did you not try that one which was posted here the other day?
<conchuod> smaeul: what is story with that timer patch then? I saw some stuff on the opensbi repo about handling it the way anup suggested & I'd like to get RCU stall detection back working for me again.
<conchuod> But I am not really au fait with what the d1 is doing there, so not sure if I should push for the revert or not.
<another|> conchuod: I did. still get Illegal instruction from qemu
<conchuod> Stupid question I am sure, but I assume your QEMU properly supports vector?
<another|> I suppose so. It's 7.1, SBI reports it, /proc/cpuinfo reports it
<another|> though I've been wondering if the problem might be somewhere in qemu
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<smaeul> conchuod: the subset of the CLINT functionality needed by the time extension (MTIMECMP) is available; just the MTIME register is missing
<conchuod> Oh, I see.
<smaeul> so you can put the CLINT in the DT (and it used to be there, until I found out it was noncompliant from the HDL), and drivers/clocksource/timer-riscv.c will work
<conchuod> What do we do about the suspend though.
<smaeul> I wrote the patch while implementing cpuidle, because playing with the clockevent priorities caused the CPU to get stuck in the idle state
<conchuod> Does Anup's proposal do anything for you on that front or is it still unresolved?
<smaeul> adding the DT property would be more about fixing your issue, no?
<smaeul> the C906 can't use the property anyway, because its timer gets reset
<smaeul> or really, s/the C906/upstream OpenSBI on the C906/, because the SBI implementation could choose to use a timer that doesn't get reset
<conchuod> I mostly read those emails either after midnight or before 0700, so maybe I misremember things - but adding a property for the pre-existing case seems a bit ehh?
<conchuod> I've been really busy so I've lost track a little bit, I'll have another read through all of that stuff again this week.
<smaeul> the property he proposed was riscv,timer-can-wake-cpu -- it's progressive enhancement, with the base case being not to assume anything about the timer capability
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<smaeul> though it would be possible to go the other way, like arm,no-tick-in-suspend
<conchuod> Ye