<mps>
I tested boot with uefi on visionfivev1 few months ago and it worked in first stage but didn't finish because grub in alpine linux have bug, and I didn't tried later
<mps>
yes, I used this version
<rneese>
I have not touched alpine
<mps>
so I think I have to wait for next grub or try to patch it
<rneese>
I have only used the ubuntu img we have as its wha I am working on
<rneese>
if you run that file you should be able to run the ubuntu img
<muurkha>
tusko: AMD can't produce any chips at all
<pedja>
amd is doing fairly well, considering they have to 'compete' for tsmc time with deep-pocketed nvidia and apple
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<muurkha>
but I did intentionally separate out design and assembly from fabrication in my remark, tusko ;)
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<muurkha>
PRC is in sort of the same position as AMD except that USG won't sanction AMD
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<tusko>
AMD are also mega social justice warriors
<tusko>
...like China
<conchuod>
?
<conchuod>
What does that even mean lol
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<dh`>
"china" and "social justice warrior" are ...interesting concepts to put together
<conchuod>
And what makes AMD "social justice warriors"
<dh`>
jrtc27: re pte use bits yesterday, I was forgetting that you'd need to sfence.vma after clearing them. but even with that, I think it still sucks
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<dh`>
bah
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<dh`>
jrtc27: re pte use bits yesterday, I was forgetting that you'd need to sfence.vma after clearing them. but even with that, I think it still sucks
<dh`>
that is, without I was thinking you needed to snoop page table writes to know when you need to set the use bits again
<dh`>
but with, if you sfence.vma on every pte you update as you're scanning, that's a lot of sfence.vmas and that probably itself sucks, plus each one causes the cpu to forget which entries it's marked so it ends up repeating a lot
<dh`>
unless you do something like suspend all threads in a process when you go to scan its pagetables so you know they aren't getting used while you're working, and then sfence.vma once at the end; but that suspend is also expensive
<jrtc27>
you can batch it up
<jrtc27>
only need to sfence.vma at the end
<jrtc27>
so long as you're careful
<jrtc27>
you don't need to suspend the threads
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<geist>
that tracks. pretty similar to ARM64 and DSB
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<dh`>
if you clear a bunch without fencing, they can be used without you ever seeing
<dh`>
then again, that race exists if you do one at a time too, it's just smaller
<dh`>
and missing a few isn't the end of the world in a normal vm system
<dh`>
though it means you want to sample more often
<dh`>
anyway, it still seems like the whole scheme is bad
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<dh`>
and it takes up two PTE bits
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<geist>
in the case of ARM you can generally be fairly slack about it *until* you start fiddling with A and D bits. riscv may have the same race if/when that gets added (i forget the current status on those)
<geist>
since you now have hardware fiddling with the same page tables out from underneath you (software) and everything is weakly ordered. the barriers suddenly get a lot more important and interesting
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<muurkha>
dh`: well, communism is nominally the ideological basis of the PRC government, and its purpose is to correct the injustices that capitalism inflicts upon the working class. but I think that's kind of theoretical; the Cultural Revolution is generally considered an unfortunate tragedy in Chinese history, not a laudable effort that just failed to go far enough
<muurkha>
but I have very rarely found it valuable to talk to people who start talking about "social justice warriors"
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<dh`>
indeed
<dh`>
(on all points)
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<muurkha>
the native instruction set is mostly just RV32C plus a few uncompressed instructions, and the other instructions trap to microcode implementations
<muurkha>
he says it's 61 flip-flops and 423 Xilinx LUTs, not counting the ROM, peripherals, and I'm guessing the registers
<muurkha>
while SeRV is 312 FFs and 182 LUTs, without C
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<muurkha>
and if you enable C, SeRV grows to 336 LUTs
<muurkha>
it's uh not very fast but faster than SeRV
<dh`>
one of these days I should figure out how to write hardware, mucking with stuff like that for hack value seems like it would be fun
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<muurkha>
I'm still a bit intimidated by Verilog myself, to be honest, dh`
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<muurkha>
in theory I understand the main ideas of digital hardware: for synchronous design you first reduce your design to a register machine (that is, with finite memory), describe the next state of each register as a pure (combinational) function of the current states of all registers (RTL), minimize the new-state function for each register according to whatever combinational logic elements you have handy (NAND
<muurkha>
gates, LUTs, 2716s, sums of products, or whatever), wire up the hardware accordingly, and then spend hours with a logic probe or logic analyzer figuring out which nets have the wrong waveforms on them and why
<muurkha>
after verifying your design in simulation, of course
<muurkha>
but it's been decades since I built an interesting logic circuit in actual hardware
<bjdooks>
my last VHDL was dealing with PCIe gen1
<muurkha>
that sounds demanding on the speed side
<muurkha>
what was the hardest part of getting it working?
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<bjdooks>
dealing with the verilog shite the vendor supplied
<bjdooks>
the internal data-bus was 16bit, so supply 2.5Gbit/sec was a lot easier
<muurkha>
with a purpose-built serdes built into an fpga I'm guessing?
<pedja>
anyone played with that intel's risc-v simulator/dev thingie?
<pedja>
d/l requires registration, which is...expected, I guess :)
<bjdooks>
yes
<muurkha>
I wouldn't say it's expected. I didn't have to register to download QEMU, Spike, or the RISC-V spec
<bjdooks>
I've been doing a bit of work with qemu for various stuff
<pedja>
expected from Intel bearing 'gifts', I meant
<bjdooks>
hmm, registration remidns me to prod about riscv summit
<pedja>
is that where the 'state of the risc-v ecosystem' talk is given?
<muurkha>
bjdooks: so I guess if yosys had existed it would have made your life a lot easier except that it doesn't support Xilinx serdes (or officialy xilinx anything)
<bjdooks>
yeah, proprietary fpga stuff is just nasty
<muurkha>
this RV32C-plus-microcode approach seems pretty appealing to me
<muurkha>
I guess you could probably implement a smaller set of instructions and still have it work with lower performance but at some point it will stop getting smaller if you include the microcode for the missing instructions in your cost metric (which the 61 FFs and 423 LUTs doesn't)
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