sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<smaeul> conchuod: I see what's going on. I forgot about the other quirk of not supporting 64-bit MMIO
<smaeul> I'm able to boot without sun4i-timer by merging https://github.com/Icenowy/opensbi/commits/c900-clint and using the right compatible
<conchuod> Cool, I'll try it tomorrow
<smaeul> or in other words, the hang has nothing to do with Ethernet. Ethernet just happens to probe around the first time Linux tries setting a timer
<conchuod> Similarly in uboot I assume
<conchuod> At least, Ethernet there was not working for me either w/ the sunxi timer bode disabled
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<smaeul> that's with adding the CLINT to OpenSBI and the DT, and lowering the sun4i-timer rating so that riscv_clocksource gets picked instead
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<smaeul> the behavior is exactly what I would expect: https://tpaste.us/en8z
<smaeul> conchuod: what should I be looking for to know if I have "broken timer behavior"?
<smaeul> do you have a test program I can run, or was that the one you were having trouble with earlier?
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<conchuod> Sorry smael, I fell asleep
<conchuod> I dont have enough source to recompile it unfortunately
<conchuod> But apparently it does run even if thr hart count is wrong
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<conchuod> smaeul: Aye, sbi timer is not working on the d1 either with C3STOP enabled lol
<smaeul> what do you mean by not working?
<conchuod> The exact same stuff that I see on fu540/fu740/mpfs where clock_nanosleep() is locked to integer multiples of a jiffy. So with HZ=250, a timer set for 5 ms returns after 8 etc
<smaeul> ah, ok
<conchuod> breakfast & then I'll reply to the thread with something more fleshed out :)
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<smaeul> conchuod: so this whole time I thought the hrtimer broadcast clockevent was available. turns out it relies on being registered by arch code. try applying 9358d755bd5cba8965ea79f2a446e689323409f9 to arch/riscv/kernel/time.c and see if that helps
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<smaeul> or its copy/paste 022eb8ae8b5ee8c5c813923c69b5ebb1e9612c4c ;)
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<smaeul> with that change, usleep(100) does the right thing in both SMP and UP configs
<smaeul> I really should have made the connection that jiffy-accurate timeouts == broken oneshot earlier...
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<conchuod> You want me to make a patch for that or will you?
<conchuod> b/c yeah, fixes it for me :)
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<Esmil> conchuod: i think you forgot to add linux-riscv to the actual patches of "RISC-V interrupt controller select cleanup", or am i just confused?
<conchuod> From: Conor Dooley <conor@kernel.org>
<conchuod> Palmer Dabbelt <palmer@dabbelt.com>,
<conchuod> Anup Patel <anup@brainfault.org>
<conchuod> To: Marc Zyngier <maz@kernel.org>,
<conchuod> Cc: Thomas Gleixner <tglx@linutronix.de>,
<conchuod> Paul Walmsley <paul.walmsley@sifive.com>,
<conchuod> Albert Ou <aou@eecs.berkeley.edu>,
<conchuod> linux-kernel@vger.kernel.org,
<conchuod> linux-riscv@lists.infradead.org,
<conchuod> Conor Dooley <conor.dooley@microchip.com>
<conchuod> They're in patchwork so idk
<Esmil> ok it's probably just me then, thanks
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