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<drewfustini>
For those using RISC-V systems with PCIe, does Linux directly handle enumeration of devices and BAR assignment?
<drewfustini>
Most documentation I can find is very x86 centric. I am uncertain if firmware has to handle this on non x86 platforms too or if Linux can just do it itself
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<bjdooks>
drewfustini: the unmatched, you can either get uboot to do it or just ignore pcie in uboot and have linux scan the bus
<bjdooks>
i think in both cases linux will assign pcie bus nd addressing
<drewfustini>
Great, thank you
<drewfustini>
conchuod: does PolarFire SoC work similarly?
<conchuod>
yeah, we ignore it in u-boot and then linux picks stuff up during boot.
<conchuod>
the dt only gets the root port address & the things on the bus are discoverable
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<drewfustini>
Good to hear. I had the misconception that Linux expected from where to handle the enumeration and BAR assignment
<drewfustini>
s/from where/firmware/
<bjdooks>
linux has had comprehensive pci/pcie bus init code for a long time
<bjdooks>
there might be a cmdline flag to force it to use the firmware setup values already
<drewfustini>
Thank you
<drewfustini>
The context is I'm working with a new SoC with DesignWare PCIe dual mode controller. the vendor's firmware currently only handles PCIe end point functionality.
<drewfustini>
I've been trying to figure out what needs to be added to the firmware for Root Complex mode. It's good to know the firmware can skip dealing with enumeration and BAR assignment as Linux can handle this
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<jrtc27>
same is true for FreeBSD
<muurkha>
cool
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<drewfustini>
Good to know, thanks
<bjdooks>
yeah, linux will need a dw-pcie wrapper and the appropriate phy setup
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<palmer>
drewfustini bjdooks there's also usually some bits near the DW IPs that you need to set up, there's a bunch of examples upstream
<bjdooks>
yeah, the glue should basically ensure phy and core are ready before the dw-core gets called
<palmer>
yep
<palmer>
so stuff like interrupts/clocks are almost certainly necessary, maybe stuff like pinmux/power/mmio/DMO
<palmer>
*DMA
<palmer>
the SiFive stuff has the bare minimum, but if you're working something more production-targeted then it's probably better to find a similar arm64 design
<bjdooks>
some of that comes from the dt, a bit will be the phy
<palmer>
ya, but last time I was messing with this there was vendor-specific glue to get those phy control bits plumbed through -- maybe something changed, though?
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<bjdooks>
yeah, that's the wrapper code that gets the bits like the phy sorted, and maybe power/reset/etc
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<drewfustini>
I was hoping to be able to use the "snps,dw-pcie" compatible in pcie-designware-plat.c but I need to get more into the specifics.
<drewfustini>
It seems though that many vendors end up creating their own driver even though they seem to be licensing the same DWC IP
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<palmer>
drewfustini: the DW stuff is a bit of a mess, are you even allow to publicly say it's DW?
<drewfustini>
Not sure about what's allowed to be said publicly. I have access to all the docs but I need to figure out if what is already in the kernel is a good match for the DesignWare IP that is the SoC I'm working on
<drewfustini>
I was hoping so but I am guess there is a lot glue and quirks I'll need to add
<palmer>
the docs I had were very-NDA
<palmer>
you should probably check with some folks before posting stuff publicly ;)
<drewfustini>
Similar situation with getting eMMC working with the DWC MSHC in this SoC. There was a generic compatible for it but I had to make several tweaks and enable lots of quirks to get it to work
<palmer>
yep, it's always a mess
<palmer>
every time I've had to deal with this before there's months of silly "can we post this" discussions, and then it's just some little quirk that a handful of other folks forked the driver for to avoid calling out
<drewfustini>
Oh yes I mean I have access to all the NDA docs that a SoC vendor would. I'm trying to assess how much new code will need to be written. It seems lots of vendors use this IP but unfortunately it seems most create their own driver to account for the glue
<palmer>
yep, and that makes it super hard to figure out which flavor of the IP each one supports and whether you can use it ;)
<drewfustini>
My experience so far with the support from snps has been very poor :)
<drewfustini>
Yeah, in a perfect world, people could list the exact IP version in the kernel driver along with the configuration parameters they used in the IP generator :)
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<jrtc27>
yeah I don't understand why the glue for dw pci stuff can't be standardised...
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<muurkha>
jrtc27: might be hard to standardize it if DesignWare gags the people who would have to agree on the standard so they can't talk to each other
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