sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<bjoto> Hmm, lore.kernel.org is sad?
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<Tenkawa> bjoto: what do you mean?
<Tenkawa> Its at least "partially" working here
<bjoto> Tenkawa: No new mails at https://lore.kernel.org/linux-riscv/ for a while, but seems to be working now...
<bjoto> Ya, seems back here as well.
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<Tenkawa> Yeah... the indexer looks a bit lagged
<bjoto> I'm using l2md for the mailing lists, so when lore isn't working I get worried
<davidlt> It seems to be on/off, with kernel.org today (at least for some hours)
<Tenkawa> davidlt: yeah thats not good...
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<meowray> sorear: CREL with implicit addends compacts .debug* sections really well. many relocations need one single byte in the .crel.* section. I plan to propose -Wa,--implicit-addends-for-data to switch to REL or CREL-implicit-addend for sections that only contain data relocations. i believe this should work with R_RISCV_{ADD,SUB,SET}* as well, but i need to check binutils' support for REL
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