sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<another|> Is there an explanation of zimm[10:0] in the vsetvli instruction?
<unlord> another|: the official PDF specs leave a lot to be desired
<lu_zero> just to reiterate what I told unlord, having a language server to quick lookup the documentation might be a good idea ^^
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<sorear> another|: it's verilog syntax and matches the use of uimm in the definitions of instructions like c.sw
<sorear> unlord: which risc-v spec would you say is the best and why? i find that they're getting _worse_
<unlord> sorear: did I say any of them were?
<sorear> no, but they're very different from each other and if you can't tell the difference between them you can't help find a good outcome
<sorear> even if none of them is _good_ one of them is still the _best_
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<dh`> that's not automatically true :-)
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<geist> the vector specs are particularly dense, it's clear that different parts of the riscv specs are written by different people
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<sorear> I'm hoping that people don't see things like Zc and CHERI as "good" just because they have a separate page for every instruction
<sorear> longer specs are automatically better right?
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<lu_zero> sorear: the only good specs are those machine parsable...
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