sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<sorear> is there a known reason why the t-head opensbi doesn't use t-head's remote fence hardware to implement the sbi remote fences?
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<guerby> "The world's first RISC-V servers available in the cloud.
<guerby> Taste the new open processor architecture now.
<guerby> Will you take the risk?"
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<geertu> guerby: Reminds me of the motto of the "safety and security at work" council at a former employer: "no risk, no fun"
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<sorear> riscv32 finally in a realized version of musl libc
<palmer> what does "realized" mean? I though musl had support for a while?
<sorear> s/realized/released/
<sorear> riscv64 had support for a while but riscv32 stalled, at first because the kernel abi wasn't stable and later because it was to have been musl's first time64 arch
<sorear> *32-bit time64
<sorear> then musl 1.2.0 made all 32-bit architectures time64 but riscv32 was still a bit weird for lacking time32 syscalls
<sorear> there was an out of tree patchset for riscv32 written by me in 2020 and mostly maintained by khem since then. I no longer remember what, if anything, was there before 2020
<Tenkawa> Anyone familiar with a standalone sdcard.img type build for the Milk-V Mars out there yet?
<Tenkawa> (specificly the CM model)
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<Tenkawa> Found a procedure using a RPI IO Board to hopefully unscramble whatever I did to my cm itself
<Tenkawa> We shall see
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