sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<smaeul> is there an implementation of the SBI firmware feature extension anywhere?
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<smaeul> sorear: it's more than 20-50 instructions to restore all of the IMSIC and PMU state if that gets lost
<smaeul> but yeah it wouldn't be too hard for M-mode to pretend a state is retentive; OpenSBI has the save/restore code anyway for domain switching
<smaeul> the trickier part is handling hardware that loses its timer state (Sstc or CLINT) during nonretentive suspend. firmware would need some concept of a global/broadcast timer that doesn't interfere with the TIME extension
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<Esmil> smaeul: sorry, i didn't quite get that. is there a patchset for 6.9 you want me to test on a jh7100?
<smaeul> there's no patch yet, but I plan to write one
<Esmil> ah, i see. i'll look for that then
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<sorear> smaeul: what does linux do about IMSIC and PMU state? PMU state might get restored across context switches, but per-user-process stuff like senvcfg gets touched so i'm not sure that means anything, dropped IMSIC interrupts sounds like a much bigger problem
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