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<jrtc27>
sorear: alex is ex-cambridge still working with us
<jrtc27>
andres and tariq are codasip with whom we're closely collaborating
<jrtc27>
I'm overdue to read their draft though
<jrtc27>
and the other chair of the sig and tg, simon, is cambridge
<jrtc27>
the basic gist is codasip have formulated a draft specification based on various discussions with us
<jrtc27>
and we'll iterate on that
<jrtc27>
though the extension names are of course invalid...
<sorear>
at a first skim, i want to try to get the cap-mode auipcc to be more like an aluipc/adrp/l.adrp/pcaladu12i, and i think there's a more consistent way to handle capabilities in V
<jrtc27>
capabilities in V is a big unknown because nobody's tried it yet
<jrtc27>
diverging with auipcc should only be done if really necessary IMO
<jrtc27>
as it's added complexity
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<jrtc27>
so IMO cheri shouldn't be an opportunity to do a risc-vi, as much as there are design decisions I disagree with in risc-v too
<jrtc27>
but that's just my personal opinion
<sorear>
I dislike what ISAv9 has to say about vectors because it leaves so little wiggle room that you _can't_ do a proper integration
<sorear>
riscv-cheri#2 seems better but until I figure out how to build it or otherwise read it in order I'm not certain of my readings
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<sorear>
I see your point with risc-vi although to me auipc is less "fundamental design decision" and more "it would be completely reasonable for auipc and aluipc to coexist, except we're all out of 32-bit major opcodes, it's uncertain if a 48-bit opcode map will ever be ratified, and if you want to use a 64-bit sequence for data segment access you can already do that"
<jrtc27>
I think it also makes cheri-on-rv32's auipcc even worse when it comes to representability issues
<jrtc27>
but haven't fully thought through that one
<sorear>
i'm questioning the frequency of use of a lot of the instructions cheri-x86-64 puts in the one-byte map
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<muurkha>
that all sounds reasonable to me
<sorear>
the PR, the discussion, both, neither?
<muurkha>
the discussion, sorry
<muurkha>
probably I shouldn't say anything because you and jrtc27 are both far better informed tthan I am
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<sorear>
i'd argue that high-quality implementations of rvv *should* special case strides of +1, because fortran array types always have a stride and if a programmer tries to pass an array to a subprogram, the subprogram will wind up doing stride=1 accesses. this argument may extend to 0 and -1, but there should probably be some attempt to get data, i don't know how common reversing an array with a section is in practice
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<muurkha>
sorear: is it possible that the non-special case might already be enough to put the bottleneck elsewhere? like in your cache for example
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<A1ice>
Has anyone successfully implemented full disk encryption on allwinner d1 platform?
<A1ice>
I want to try to use the D1 device as a terminal-only device for my use
<muurkha>
it runs mainline Linux, right? so you can just use dm-crypt in the standard way?
<courmisch>
if it's anything like the other TH C9xx, it runs vendor kernel
<A1ice>
I'll try it first
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<muurkha>
courmisch: thanks, I didn't realize that
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