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<sorear>
jrtc27: which cores support accessing full-width capabilities through an extended abstract command? I checked CTSRD-CHERI/Toooba and /Flute and both of them seem to have an XLEN-bit path between the core and the DM
<jrtc27>
yeah we never did the work to make debugging baremetal a thing on hardware
<jrtc27>
mostly because extending openocd was terrifying
<jrtc27>
the hardware side of things is relatively boring
<sorear>
trying to walk a fine line between "asking people who don't understand me why they don't understand me because I can't figure out how I've been screwing up so consistently" and "being gratuitously rude to people who don't understand me"
<sorear>
i see
<sorear>
"no baremetal on hardware" implies that it does work in some capacity on an architectural simulator, presumably qemu, how much of the debug spec is exercised in that way?
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<jrtc27>
none; qemu provides a gdb stub directly
<jrtc27>
#60 did lack context for what the quote was from (but it's not that hard to guess and confirm it)
<jrtc27>
#58 I don't know why tariq went on that direction for the second half of his message, perhaps just to justify why metadata from pcc is what he believes to be the right thing
<jrtc27>
(though I disagree about there not being a use case for a table of capabilities)
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<sorear>
jrtc27: how do the latencies of your capability operations compare to 64-bit integer adds or float adds? Do you have to extend any of them over multiple clock cycles?
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<arichardson[m]1>
That depends on the instruction and implementation. Adds + basic capability field inspection/manipulation should always be a single cycle, but it's possible that the ones that need to compute new bounds could take two cycles (setbounds/buildcap)
<sorear>
interesting. hopefully it's close to an add in physical (ps) terms and you're not just stretching out the cycles because speculative vipt caches give the security team hives
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<jrtc27>
sorear: Morello has capability add immediate and (possibly shifted) register as both single cycle at 2.5 GHz
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<sorear>
When you're doing compartmentalization within a process on CheriBSD, how does it restrict system call activity by compartments that aren't supposed to be doing them?
<jrtc27>
historically we did it with a software permission bit
<jrtc27>
currently it's not enforced and is a known gap
<jrtc27>
on morello you have executive/restricted that can also be used,
<jrtc27>
but the existence of restricted mode makes the abi kind of gross to deal with, so not a fan of it
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<sorear>
gross in what way?
<jrtc27>
code in executive mode needs to see both sets of stack+ddc+thread registers in its ucontext etc structs
<jrtc27>
code in restrictive mode needs to see just the restricted ones