sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<bjoto> Hey all, I moved the Linux kernel patchwork runners from the 2 dedicated machines to GKE/Autopilot (fancy Google k8s thingy). Hopefully the build throughput will be better. On top of that, I've added a major workflow for Linus' master, riscv for-next/fixes, and Palmer's for-next/fixes staging. This builds 140 different configurations, and tries to boot all the built kernels (Like
<bjoto> https://github.com/palmer-dabbelt/riscv-systems-ci but does UEFI as well). I did a horrible python hack that can scrape the results from github: https://github.com/bjoto/linux-riscv-gh-utils
<bjoto> (Never deploy on a Friday and all that...)
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<[exa]> bjoto: friday deploys are the most educative!!!1
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<bjoto> Love that positivity ;-)
<bjoto> Problem + k8s = 2 problems...
<Tenkawa> I wish I could've deployed on a Friday when I did builds for a living.... for me it was always weekends + holidays only
<[exa]> rule 1 of friday deploys: you don't ask if you can do friday deploys
<Tenkawa> LOL
<Tenkawa> [exa]: nice....
<Tenkawa> Actually we could've only dreamed of having this architecture in 1996
<Tenkawa> lol
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<[exa]> yeah all testing was completely random by then, `make test` and hope
<Tenkawa> Yeah... most here won't be familiar with it but I used nmake on svr4 back then.. not even Linux/GNU make yet....
<[exa]> yayy.
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<sorear> wondering again how much longer we'll get away with "ratified specs cannot have errata, even if they're unclear or self-contradictory"
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<sorear> (Svadu D bit updates are kind of broken for sc instructions, since the D bit update does not happen unless there is a write, it cannot happen until the sc is committed to either succeed or fail, but the D bit update is ordered before the sc and thus inside of, potentially interfering with the lr/sc pair)
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