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<cousteau>
sorear: heh, good point
<cousteau>
...Of course, Arm's "free as in free game" cores are released with the condition of "don't use for reverse engineering, yada yada, or for benchmarking this core against others without explicit permission from our side".
<muurkha>
cousteau: I see
<muurkha>
free as in free mattress
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<cousteau_>
muurkha: I wouldn't call it that... With the mattress at least you can do whatever you want afterwards
<cousteau_>
sorear: btw at some point I guess I'll have to learn where a core ends and where a processor starts
<cousteau_>
...well, where the rest of the processor / SoC starts
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<cousteau_>
If I am to take rocket-chip's description literally, the "core" is one thing (includes ALU and also maybe FPU etc), the "tile" adds L1 cache and PTW, and the, um, "system"? adds system bus, L2, BootROM, some "internal" peripherals such as interrupt and debug modules, and external connection to RAM and possible "external" SoC peripherals
<cousteau_>
I don't know where the FPU, MMU, and PMP units would be.
<cousteau_>
(But I know it's somewhere within the inner side of the caches)
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<muurkha>
cousteau_: well, possibly the mattress will do things to you afterwards that you don't want
<muurkha>
depending on what you do with it
<muurkha>
which seems like it might be the situation here
<muurkha>
the bit-tech page makes it sound like they're only licensing M1 and M3 for Xilinx FPGAs
<muurkha>
the M3 is from long enough ago that all patents applicable to it should be dead, right?
<gurki>
unlikely
<bjdooks>
I think the only stuff out of patent is the early arm32
<bjdooks>
and even then arm are like disney and will sue
<cousteau_>
muurkha: ah
<cousteau_>
...sounds to me like the mattress comes with an std for free! Two for the price of none!
<gurki>
oh i never said that ... "i want to do research xyz" might actually be a good enough reason. phrasing is important :3
<gurki>
(regarding our earlier discusion)
<cousteau_>
gurki: ah... Well, I wasn't quoting you, just quoting what I imagine would happen
<cousteau_>
Also, an NDA won't do because I want to D the hell out of it
<cousteau_>
bjdooks: I vaguely remember "ARMv2" being "the last ARM that was available as something something free"
<cousteau_>
For some definition of "something something"
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<muurkha>
cousteau_: you almost certainly can't get AIDS or herpes from a mattress, but lice, scabies, fleas, measles, and chicken pox are possibilities
<muurkha>
anyway patents are only supposed to run for 20 years from filing and in the US you only have a year after publishing or selling the "invention" to file. in the rest of the world you have 0 years
<muurkha>
so in theory anything on sale as of 21 years ago should be free and clear
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<muurkha>
which is maybe part of why ARM wants to stipulate in their contract for the M1 and M3 that you won't use them to find ways to invent around ARM's patents
<muurkha>
21 years ago now is early 02003
<muurkha>
the Cortex-M3 was introduced in 02004 (the first Cortex-M I think) so you might have to wait a year or two
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<geertu>
muurkha: Initially, I misread "patents" as "patients", after your comment about mattress disease spreading ;-)
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<muurkha>
geertu: heh
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<cousteau_>
geertu: haha
* cousteau_
staring at muurkha's 5-digit year format
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<geertu>
cousteau_: Isn't that an SMD package size? ;-)
<geertu>
Or octal
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<cousteau_>
geertu: I definitely thought of octal
<cousteau_>
Years 1027 and 1028
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<muurkha>
heh
<geertu>
cousteau_: Patents have expired
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<cousteau_>
Except if they're from Disney
<cousteau_>
Patent registered in 1027, won't expire until 2027 with the current pushed legislation :D
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<bjoto>
Hmm, sifive-u54 and virt sometime fail to boot on latest riscv/for-next: 17a4608c5ada ("Merge patch series "riscv: support kernel-mode Vector"")
<sorear>
cousteau_: you'll notice that the published SPECxxx results are for _systems_, not even processors
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<sorear>
cousteau_: a core approximates "a single instruction-fetch unit and all private resources connected to it" but the edges are very fuzzy and subjective (private caches obviously but also stuff like Bulldozer's clustering)...
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<sorear>
does anyone else think that SBI SSE is painfully overcomplicated relative to the function it achieves