<xypron>
Both eMMC and SD card are scanned. The .itb must be on partition 2. See configuration.
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<xypron>
drewfustini: Do you have eMMC installed?
<xypron>
drewfustini: Which version of U-Boot are you using?
<xypron>
We have a preinstalled image if you want to run from SD card. The installer is meant for installation on a different block device. It cannot install to the boot medium.
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<xypron>
I have updated the wiki to use 'load mmc 1:1' in the instructions.
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<yae>
What are ways a newbie programmer can contribute/get familiar with the RISCV architecture and ecosystem?
<muurkha>
programming
<muurkha>
sorry, I shouldn't say anything on this topic.
<yae>
what?
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<muurkha>
I mean I don't know very much about teaching, and I don't remember what it's like to be a newbie programmer.
<gurki>
yae: getting some code to run in a simulator (such as eg spike) should already cover a bunch of things
<gurki>
bonus points if you get the debugger to work :)
<gurki>
have a look at the asm output, compare it with the asm output of plain x86 gcc
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<[exa]>
yae: tbh, try to get some of your stuff running on any riscv hardware/vms, and if it doesn't work, writing a small fix or just reasonable bugreport helps a lot
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<rbmarliere>
yae: theres some good free resources in eDX from the linux foundation
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<chripo>
+2
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<drewfustini>
xypron: thanks for information. Those are good questions. The U-Boot was the most recent from Starfive. I'll check about the emmc. I'm getting the board today from my friend so I can try it myself.
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<xypron>
drewfustini: Debian already has a package u-boot-starfive in experimental. We should soon see it in Ubuntu Noble 24.04.
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<courmisch>
how does that even work? does it come with a custom SPL that needs to be manually flashing to SPI?
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<cousteau>
Hi, is there any website that compares benchmarks of different processors? Some googling only yielded a site that compares an obscure PassMark benchmark which I have never heard of before
<cousteau>
Seems spammy
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<sorear>
depends on the benchmark i think
<cousteau>
Well yeah, at this point I'd be happy with "a benchmark"
<Tenkawa>
palmer: I'm not too disappointed yet... when the RPI soc started out the cpu was nominal
<Tenkawa>
but it accelerated quickly
<Tenkawa>
but it did have major backing
<cousteau>
sorear: yeah I did find the ones at CoreMark once I remembered the website. Not much there though
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<cousteau>
One thing I considered was making some sort of framework for doing these comparisons theoretically
<cousteau>
Like, get the RTL of example implementations of both an ARM and a RISC-V, synthesize them into a netlist, and calculate the approx area (resources) and max frequency (logic levels)
<cousteau>
Then use cycle-accurate simulations to run a benchmark
<gurki>
synthesized netlists might bot relate well enough to chip area
<gurki>
they are more of a ballpark
<gurki>
not*
<cousteau>
Energy consumption might be interesting too but harder to figure out, maybe too hard
<gurki>
youd also typically provide that timing info to the tool and itll try to make it happen
<cousteau>
Wouldn't that only matter when routing, mostly?
<gurki>
routing might require more additions
<gurki>
but its already quite relevant for synthesis
<gurki>
you can save area if you give slack on timings
<cousteau>
I don't think I'll consider routing at all in this idea of mine...
<gurki>
itll also strongly depend on the pdk :3
<gurki>
your idea requires a fair share of tinkering
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<cousteau>
gurki: for example? One thing I did think of is that if cell A connects to cells B and C, but B is far away in this direction and C is far away in that direction, it may make sense to duplicate the path, adding redundant duplicate logic just to split the path into two
<cousteau>
But that only makes sense when placing
<cousteau>
Also... my ASIC fu(*) is a bit rusty, but aren't timing constraints only used AFTER synthesis (RTL to netlist)?
<gurki>
depending on how fast your alu is supposed to be youll need a different level of sophistication in your adder trees
<gurki>
even more so for division
* cousteau
(*) I touched Cadence tools ONCE, like 2 years ago, and have forgotten pretty much all of it, which was very little to begin with
<cousteau>
Fair enough
<gurki>
youll provide timings to both the synthesis and the pnr tool
<cousteau>
Just today I've been trying to figure out how to optimize an adder
<gurki>
heh :)
<gurki>
the stuff eg dc shell does is pretty mindblowing
<cousteau>
Yeah that doesn't happen with FPGAs, which are more like my field
<cousteau>
Or not enough to be necessary, at least
<gurki>
im more of an asic person bud id expect them to do similar magic
<gurki>
its obv more limited
<gurki>
you cant just place that magic dw block
<cousteau>
But... I think my idea for estimating number of logic levels can give a good approximation
<cousteau>
Or just speed directly
<cousteau>
At least for a comparison between two platforms
<cousteau>
For example, some Core-V cores and, uh, an ARMv2 which if I recall correctly was the last one with a disclosed source [verification needed]
<gurki>
you can get access to a lot of these with appropriate ndas
<gurki>
youll need good reasons though
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<cousteau>
Is "I want to prove that your shitty commercial closed-source core sucks and that RISC-V is way better" a good reason? :) yeah I didn't think so either
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* cousteau
tries to think of a list of freely available cores for his possible test... In addition to RV and OpenSPARC, I just found out that Cortex M0 and M3 are available too!
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<cousteau>
Oh and Power ISA too
<cousteau>
The main problems with my idea are that neither the benchmarks nor the methodology for estimating the theoretical area and speed are going to be accurate
<cousteau>
Like, what benchmark do I use? CoreMark? Dhrystone? One of the other bazillion ones? Is there even a benchmark that is considered "good" and widely accepted?
<jrtc27>
spec
<jrtc27>
the least bad these days
<jrtc27>
coremark is a waste of time for most purposes
<jrtc27>
it fits entirely in a modern L1 cache
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<muurkha>
cousteau: oh hey, Cortex-M0 and M3? that's fantastic! where?
<muurkha>
jrtc27: anything that doesn't fit entirely in the modern L1 cache of a big processor won't fit in the entire RAM of most processors
<cousteau>
jrtc27: yeah my impression was that Coremark does a fine job at advertising itself and not much more
<jrtc27>
muurkha: the lesson here is that there is no one size fits all benchmark that can range from microcontrollers to big iron
<cousteau>
muurkha: no idea, I just found it in Google. From 2018. Also probably not RTL, just "here use this netlist, for free"