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<ralphtucker>
is there anyone who can tell me what is the purpose of Ecall instruction and how to implement it ? Is it necessary to implement csr's first in order to implement ecall?
<courmisch>
how it works is explained in the privileged isa spex
<courmisch>
and yes, at least in practice
<ralphtucker>
yes it is explained in the privileged isa spec, but i don't understand it working through that, is there any other way to understand it?
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<sorear>
from U-mode's perspective, ecall is a black box that does stuff defined by the execution environment (e.g. on linux it behaves as a0 = syscall(a7, a0, a1, a2, a3, a4, a5, a6); )
<sorear>
from a hardware perspective, ecall is an illegal opcode, except that it sets xcause to (8 + priv) instead of 2 and delegates appropriately for the xcause value
<sorear>
does either of those help?
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<muurkha>
it's probably worth mentioning that in a RISC-V emulator for U-mode code, you can implement it without implementing CSRs, which is implicit in what sorear said
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<courmisch>
any compiler person? what's the stance on vsetvli inside inline assembler? is the compiler supposed to assume that vl and vtype are always clobbered?
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<palmer>
courmisch: can you file a GCC bugzilla? we've really screwed up the vector stuff
<palmer>
we probably need a clobber for vl or vconfig or something
<palmer>
ya, I wouldn't really count on it working though. So if we've got examples of actually using it that'd be great, it's something that needs to get tested properly
<courmisch>
oh yeah I should have tried instead of asking
<courmisch>
GCC has both "vl" and "vtype" clobbers
<palmer>
oh, so you're not getting bad codegen or something?
<courmisch>
no I was just wondering
<palmer>
ah, ya, OK. There's some other stuff in vconfig too
<palmer>
I'd be pretty hesitent to trust a lot of the vector stuff right now, it's all pretty broken (at least in GCC)
<palmer>
looks like we don't have any tests for the inline asm clobbers, unless I'm missing some? So I guess even if this works it's probably worth putting some examples somewhere
<courmisch>
to test this, you'd need to mix intrinsics and inline assembler, and I am not familiar with the earlier :/
<palmer>
ya, ignoring the intrinsics the right way to go
<palmer>
I'll add it to the TODO list... ;)
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<courmisch>
I hate SIMD intrinsics in general and the RVV ones in particular. I respect that some people prefer that over outline assembler, but count me out.
<solol>
Ooh, I just got my 500,000 device universal remote
<solol>
I wonder what that's got.
<solol>
SofaBaton X1
<palmer>
courmisch: ya, I kind of only use the intrinsics when I really have to -- usually I try and just massage things to get what I want out of the compiler, or if it's really fancy then just proper assembly. I had some luck with some Intel stuff years ago, but the RVV ones are particularly awful
<courmisch>
to be fair, I don't know how else they could have done them. But that's all the more reason to stick to outline assembler
<courmisch>
and the RVV ABI is actually easy and convenient to work with
<courmisch>
*unlike* NEON
<solol>
What's RVV
<jrtc27>
RV = RISC-V, V = V(ector) extension
<solol>
How do you pinpoint how many of any particular registers are available on a chip?
<solol>
oh ok
<jrtc27>
you're asking the wrong question, probably
<solol>
is it in the manual or something idr.
<solol>
You can't just use 4ghz @ max...
<jrtc27>
?
<courmisch>
plus IMO intrinsics are in a weird position where you should (typically) try to maximise register utilisation... but the compiler hides them from you, so uh?
<solol>
Are those registers? Are they virtual and not like I'm thinking?
<jrtc27>
I don't think anyone here understands what you're asking or thinking about
<solol>
I thought CPU's had set amounts of each type of register for the RISCV setup or x86 or 64 / etc...
<solol>
It's not a CPU with ~Billion transistors that just do anything, right?
<jrtc27>
can I suggest you go find an undergraduate level introduction to computer architecture course?
<solol>
There's a reason for ASIC design or the algorithms ...
<jrtc27>
you seem confused
<solol>
I'm not exactly confused.
<solol>
I'm just trying to catch up real quick...
<jrtc27>
you're asking questions that show you don't really understand the fundamentals
<solol>
u guys were talking about SIMD i figured it was a good time...
<jrtc27>
and as such the questions are strange
<jrtc27>
it's hard to answer a question that doesn't entirely make sense
<solol>
Each chip was built with an algorithm for how things are placed on the chip.
<solol>
How do you count the registers for any CPU?
<jrtc27>
again, your questions do not make any sense
<jrtc27>
please go educate yourself
<jrtc27>
I don't want to have to ask a third time
<jrtc27>
if you want to learn about the fundamentals of computer architecture there are countless online resources available
<solol>
Why are you talking like this at all?
<solol>
I even used your own words, 3 times.
<solol>
You're even an operator here!
<solol>
How do you find a chipsets algorithm is too hard?
<solol>
Because it definitely makes sense.
solol was banned on #riscv by jrtc27 [*!~solol@user/solol]
solol was kicked from #riscv by jrtc27 [Your behavior is not conducive to the desired environment.]
<jrtc27>
if people think that's too harsh I'm open to retracting it, just don't want to see this channel filled with jibberish that sounds like it could have come out of some crappy LLM
<courmisch>
it was harsh, but I can't deny that they were obnoxious, and also, earlier, completely off-topic
<sorear>
are they PMing anyone other than me?
<jrtc27>
me
<jrtc27>
maybe better to let you deal with them than me?
<courmisch>
not me, but I don't remember if I've blocked nonregistered users
<Tenkawa>
Esmil_: Well I've only noticed one odd side effect so far in testing that 6.7-rc source. The IO rate on the NVMe transfers have dropped back down from 300mb/sec to 180mb/sec and so far no obvious sign of why between it and 6.5.11.
<Tenkawa>
I'm comparing settings and the dts currently to see if anything looks really obvious
<Tenkawa>
(kernel settings)
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<palmer>
IMO that's not bad worthy
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<Tenkawa>
palmer: was that directed to me or courmisch/jrtc27?
<Tenkawa>
palmer: If it was directed to me...just odd that that the speed dropped so much between versions it seems to me...
<Tenkawa>
You can also use services to block users in certain cases (like this one) by interacting with nickserv.. much more efiiective than /mode
<Tenkawa>
er chanserv not nickserv
<Tenkawa>
if you are a chan operator
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<conchuod>
sorear: I suspect it may be the same person we banned like 200 times from #devicetree
<conchuod>
they talk tripe 24/7 and DMed me after I banned them with incomprehensible drivel.
<Tenkawa>
I was starting to wonder if it was an AI/chatbot...
<Tenkawa>
Those have been popping up in various places on IRC and Discord recently
<palmer>
whomever banned this sol guy
<Tenkawa>
palmer: ahhh ok
<palmer>
sure he's confused, but just yelling at someone for being confused and then banning them is not a great way to get folks involved
<Tenkawa>
palmer: that person was continually offtopic numerous times about things continually not related to RISC-V/computing
<palmer>
OK, all I'm seeing is a silly fight and then a ban
<mps>
also for me looked strange person (if it is person)
<mps>
"when you enter someone home be kind and follow rules these", and jrtc27 asked few times for this
<mps>
s/these/there/
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<palmer>
OK, I guess that's not really how I'm reading it? It looks to be like jrtc27 just berated somenoe who was confused, and then banned them
<palmer>
might just be me, though -- I consistently find her pretty miserable to interact with, so I'm kind of used to ignoring it ;)
<mps>
idk for sure what is really happening, just expressed my observation
<palmer>
ya, I don't know etiher; )
<palmer>
I just got poked about the ban
<mps>
also I'm not fan of bans
<palmer>
ya, I generally try and actually work with people instead
<Tenkawa>
I have the log here... The user started with comments about Xbox, "what uses RISCV", 500,000 device universal remote, "What's ARM running?", "So what do you guys use hardware scripting for?"
<Tenkawa>
They definitely were not starting "normal topics"
<palmer>
ya, sure the dude's confused
<mps>
also I, and 'ban' (ignore actually) is mostly in brain
<mps>
in my brain*
<palmer>
but then there's also a bunch of non-constructive replies from jrtc27 I'm seeing, so it's not like this is a one way thing
<palmer>
if we're going to try and take some high ground here, let's at least be reasonable
<Tenkawa>
Yeah it was abrupt indeed
<palmer>
ya
<palmer>
so if the policy is just "don't disagree with jrtc27 or you'll get banned" then let's at least write it down -- that's how much of the other RISC-V stuff works, so there's precedent
<palmer>
but RVI doesn't own this ;)
<Tenkawa>
I would've recommended a "gentler" warning first
<Tenkawa>
Another compile starts... lets see if some of these adjustments can bring back some of the NVMe io.
<Tenkawa>
6.7-rc otherwise is running nicely in my tests so far
<palmer>
ya, or even just a broader approach of differentiating between "I don't understand $THING" and "and $THING is not understood by anyone"
<palmer>
sweet. presumably you need those module fixes? I think they're OK, but I left my Yubikey at home so I can't push them until tonight...
<Tenkawa>
I put the lore fix in manually
<Tenkawa>
so I have it here
<palmer>
cool
<palmer>
it's also on my staging branch
<Tenkawa>
Whats your branch url?
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<palmer>
it's just git.kernel.org palmer linux.git
<Tenkawa>
I'll bookmark it just in case... ok
<Tenkawa>
thanks
<palmer>
ya, I can never remember the actual URL patterns...
<jrtc27>
alright enough, this is just becoming personal attacks on me. if you want to debate whether that specification action of mine was right and/or should be reverted, that's fine, I even said right from the beginning that I was open to that because I acted in the moment to quash what I deemed as spam but felt there was a chance others might disagree with it, but this is going too far and resorting to airing personal resentment towards me in public (which I
<jrtc27>
would like to hear the reason for in private if willing so I can do better at whatever has been a problem in the past, but this public channel is not the venue for that kind of thing)
<Tenkawa>
np I have them memorized now
<palmer>
I generally push stuff there (fixes/for-next), pull it on my testing box, and then push it upstream
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<Tenkawa>
palmer: you using master currently?
<Tenkawa>
ah fixes/for-next
<palmer>
I merge palmer/master locally into the tester, it's essentially just a manual gate for picking up new stuff because I don't want too much churn
<palmer>
(and palmer/master is just Linus' master, but behind a bit)
<Tenkawa>
yeah I see your tag references
<palmer>
cool
<Tenkawa>
yeah.. My copy is a bit newer atm
<palmer>
there's also palmer/not-for-next, which is where I stack up stuff that should be in other trees but isn't in rc1 and thus is causing me pain for some reason
<palmer>
ya, I'm super behind again because it's been a few weeks of chaos ;)
<Tenkawa>
Yeah that happened to me last month when I was out of the country
<Tenkawa>
I was gone for almost a month
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<palmer>
Ya, it's tough -- I had two conferences and then got sick, so kind of wiped out a few weeks
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