sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<jrtc27> solrize: yes
<jrtc27> I have one right next to me :)
<solrize> :)
<qwestion> anything liber than ice rvb or nheza boards?
<qwestion> librer
<qwestion> morelibre foss oshw
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<jimwilson_> SiFive announced end of production for the Unmatched board on the forums https://forums.sifive.com/t/sifive-update-on-hifive-unmatched-boards-in-2022/5569 though curiously mouser will still let you backorder it
<enthusi> couldnt that simply mean that yet have some in stock themselves?
<enthusi> I hope it stays supported to some extent
<enthusi> it's my main desktop :) (though I work alot on the laptop admittedly)
* gordonDrogon wonders why: li a0, bar-foo is failing with Error: illegal operands `li a0,bar-foo'
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<jimwilson_> enthusi, the announcement says they still do have some in stock from first production run, but I doubt very much
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<leah2> "Will you please please engineer a quitter cooling solution and use standard footprints for heat sinks and cooling fans." this :p
<palmer> gordonDrogon: "li" is for constants, not symbols. You probably want "la"
<jrtc27> symbol difference expressions are particularly weird when you have linker relaxations
<jrtc27> I don't think la would fare any better
<jrtc27> li a0, bar-foo should work but only if the value of bar-foo is known at assemble time
<jrtc27> if they're not then I don't think la will help you, you'd need to put it in a constant pool and load from there
<jrtc27> in some cases la a0, bar-foo *might* work if it can make it PC-relative
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<nvaxplus> I have a potentially stupid question. I know the MULHSU op exists for signed multi-precision multiplies, gcc doesn't seem to actually emit it in circumstances where it seems like it would be expected
<nvaxplus> here's an example: https://godbolt.org/z/ev9K4x9bM
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<jrtc27> mulhsu is quite niche
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<la_mettrie> is the right way to make loop counter iteration & memory address iteration in RISC-V assembly simply to use ADDI (in the context of the most basic loop)? there's no any post-increment or other supposedly sophisticated mechanism for that?
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<jrtc27> yes, no pre/post-incremenent like arm
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<gordonDrogon> palmer, jrtc27 thanks. the symbols are all in the same file and the range of the subtraction is small, so I was confused, however I solved it by another way...
<jrtc27> but are they symbols in .text and are linker relaxations enabled?
<gordonDrogon> I'll need to read up more on linker relaxations, but yes, all in .text.
<jrtc27> then yeah that's your problem
<jrtc27> it would likely have built with -mno-relax, but then you lose out on the linker relaxation optimisations
<gordonDrogon> I put .option relax in the file - no change.
<jrtc27> that turns it *on*
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<gordonDrogon> er, right - norelax - no change.
<gordonDrogon> it's not desperately important for now - it was for a loop count to zero some memory - I changed the code to simply check for >= end
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<jrtc27> hm, indeed, seems it does get rejected even then by llvm
<jrtc27> interesting
<jrtc27> I guess there are issues because you don't know how to expand li until you've evaluated the value
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<jrtc27> so it's easier to just ban symbol difference expressions entirely than try and support a subset and have to explain why some work and some don't
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<gordonDrogon> I'm finding it odd as I've used constructs like this in the past in other systems (well, ok, 6502/65816 recently) but I wonder now if it's due to sometimes 2 instructions being outputted from just one line in the code... or something along those lines.
<jrtc27> yes, that's what makes it awkward
<jrtc27> (and for rv64 you can end up with quite a lot more than 2 instructions, the ISA isn't very efficient for synthesising arbitrary 64-bit immediates, really need to just load from memory for those unless they're "simple")
<gordonDrogon> indeed. it's been some time since I last did any risc assembler (Sparc/i860) and I really don't recall what happened there when trying to load 32-bit values. I suspect the assembler/linker wasn't as "intelligent" and you had to output the instructions 'by hand' as it were.
<jrtc27> sparc didn't have any pseudoinstructions from what I remember
<jrtc27> though it's weird 20/13-bit split did make it slightly easier to construct some values
<jrtc27> uh, 22/13, even
<jrtc27> 20/13 would have been somewhat understandable
<jrtc27> but it also spent a quarter of its encoding space on the call instruction (:
<gordonDrogon> I really don't recall - I think I spent a month or 3 writing a test 'monitor' that let me test the hardware and boot OBP then that was that ...
<gordonDrogon> and half that was writing the trap handler for the sliding window register save/load...
<gordonDrogon> an I lost too many grey cells to the i860's dual instruction mode, so it's nothing more than a distant memory now...
<muurkha> sparc was all about call and return
<gordonDrogon> which was probably fine in the days when memory ran at cpu speed, but those days quickly vanished as memory didn't keep up...
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<muurkha> well, I mean, for example, register windows allow you to save and restore a call frame without touching RAM
<muurkha> most of the time ;)
<gordonDrogon> and ackermann be damned ;-)
<jrtc27> so does having a cache
<muurkha> yeah
<muurkha> although usually saving and restoring a call frame to the cache involves running some instructions
<gordonDrogon> anyway, my little system just executed it's first bytecode instruction which I'm happy with...
<muurkha> congratulations!
<muurkha> I think it's fair to say that caches have pretty much replaced register windows
<gordonDrogon> so 65816 running a byecode vm written in '816 asm running a bcpl program emulating risc-v running a program interpreting the same bytecode VM ...
<gordonDrogon> the instruction was simply 'ret' but you have to start somewhere...
<muurkha> but what I meant was that the sparc instruction set seems to me to have been designed with a very high priority on procedure calls
<muurkha> one manifestation of that was spending a quarter of its encoding space on the call instruction, and another was the register window mechanism
<gordonDrogon> muurkha, indeed - but I think it's easy to do code analysis at the time (80's) and come to that conclusion - memory was still expensve and not that much slower than the cpu's of that time...
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<jburkholder> Hi, any suggestions to get help with sipeed lichee rv?
<rm> what do you need help with?
<jburkholder> I just have the board, no carrier, I plugged in a usb c cable and some leds come on and I can see a new usb device on my linux desktop, does it emulate a usb serial port I can use the access the console?
<josuah> are you trying to run Linux on it? did you already flash an image or are you in the process of installing something in it for the first time?
<rm> jburkholder, probably not by default. I should come with a 4-pin connector to plug into onboard contacts, and get UART serial console via that
<rm> for ways to work with it over USB, check out https://linux-sunxi.org/FEL
<rm> I believe should be mostly the same from Allwinner ARM
<jburkholder> I didn't put a flash card in it, I guess that would make sense
<jburkholder> Ok, got it, so this is what's making the USB do something now, I'll check out that page, thanks
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