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<la_mettrie>
"The appeal is of RISC-V is undeniable. A common ISA means that different implementations and use cases for the ISA can tap the same core software stack, thus minimizing porting efforts to compilers, operating systems, and other software."
<la_mettrie>
I'm not sure if I understand this argument. Also other architectures have a common ISA, right?
<la_mettrie>
or is the idea here that everybody would use RISC-V...
<enthusi>
it means (afaik) if you want a specific thing being done by your CPU, design and get ratified an RISCV extension
<enthusi>
rather than brewing your own company-specific things
<enthusi>
because if YOU need crypto-stuff, make it a standard and have others (and you :) create the dev-environment around it
<la_mettrie>
riscv extensions cover stuff that other architectures don't have standards for?
<enthusi>
in part, yes. Also non-modular
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<josuah>
la_mettrie: maybe an example of context for it is MIPS switch to RISC-V
<josuah>
la_mettrie: of course ARM is that already, but maybe the point was RISC-V is an open standard
<josuah>
right after your quote:
<josuah>
> The main advantage of RISC-V is not that it is a new variation or iteration of RISC, but that it is an open ISA.
<josuah>
a less popular ISA means fewer risks of being affected by the decisions of the company owning the ISA standard
<josuah>
if ARM says, hmm, in the end we'll drop SWD and only use JTAG like everyone else -> nice, but if you have a toolset only supporting SWD...
<josuah>
I'm an ISA noob though, so ymmv :)
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<josuah>
after all, a lot of ESP32s around wifi/bluetooth/lorawan etc, are running Xtensa ISA from Tensilia (now Cadence). not an ISA made by Espressif (doing the ESP32s) themself though
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<gordonDrogon>
looks like they've started to dabble in risc-v though -the ESP32-C3 is RISC-V..
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