sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<gordonDrogon> looking at some ASM startup code which zeros all registers by first zeroing x1 (mv x1, x0), then zeros the rest with mv x2, x1 ; mv x3,x1 and so on rather than just mv x?, x0 on all of them?
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