sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<jburkholder> It looks like this support allwinner d1: https://github.com/xboot/xfel
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<jburkholder> $ sudo ./xfel version
<jburkholder> AWUSBFEX ID=0x00185900(D1/F133) dflag=0x44 dlength=0x08 scratchpad=0x00045000
<jburkholder> Yay
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<dh`> so fwiw, sparc asm did not have many synthetics, but there was/is one for loading long constants
<dh`> however, I can't find my sparc manual
<dh`> ah here we go
<dh`> set, setx
<muurkha> aha, cool
<muurkha> thanks!
<drmpeg> I still have a running SPARC here. https://www.w6rz.net/sparcsethi.png
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<gordonDrogon> drmpeg, at one point I had a pallet-load of sun4 systems, wide and tall... I (stupidly?) gave them all away...
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<la_mettrie> so there's a good chance that first risc-v laptops will be china's state backed efforts?
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<gordonDrogon> it would not surprise me.
<gordonDrogon> help them free themselves from the shackles of the western capatalistic society.. oh, wait ...
<gordonDrogon> same for russia, but I get the impression they care less for that sort of stuff having evidence of stealing pdp11's (etc.) in the past...
<gordonDrogon> hm. todays puzzle - load unaligned word - do I test for it being aligned (which is possible) then just LW or brute-force it anyway with LB, shifts, or, times 4 ...
<gordonDrogon> brute forcing it seems easier - probably faster than a test/branch since a higher portion will (probably) be unaligned anyway...
<gordonDrogon> (bytecode interpreter with data words in-line with instructions)
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<gordonDrogon> 14 instructions to brute-force it byte at a time - might almost be worth getting the compiler to word align constants if speed is an issue...
<gordonDrogon> (or use an RV system that allows for un-aligned LW's)
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<jburkholder> UltraSPARC has some other synthetics, ret and retl are synthetics
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