sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<gordonDrogon> it's a combined curse and blessing of open source - I have had some intersting times with my own open source software - nothing stops people taking it and putting it into a commercial product - the downside of that is when people ask me for support rather than the company who did the integration, so hopefully SiFive can provide support for their products.
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<la_mettrie> feels a bit counter-intuitive that system control registers have their own specific instructions while the basic instruction set was supposed to be small
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<kehvo> it wouldn't be possible to use regular instructions with them for encoding reasons, and I guess memory-mapping them wouldn't be preferrable either
<gordonDrogon> they're not instructions I've looked at yet for my emulator, but they seem to fit in OK - 6 instructions in the base block with a func3 field for each one with 'standard' rs1 & rd bits ...
<sorear> "small" instruction set isn't well defined, https://fgiesen.wordpress.com/2016/08/25/how-many-x86-instructions-are-there/
<sorear> the nature of the control/status registers is that any accesses to them have to be tightly synchronized with the instruction stream because they affect the interpretation of instructions, control transfers, etc; if they were memory accesses they'd be deeply special cases and it wouldn't necessarily be simpler
<sorear> there's really only one CSR instruction, "apply AND/OR to this CSR and save the old value somewhere", with a few cases in the decoding
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