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<gordonDrogon>
Whoever dreamt up the encoding for the offset in the JAL instruction must have been (a) drunk, (b) high (c) just evil or (d) all of the above...
<sorear>
can't rule out a/b but the optimization criteria was "minimum number of muxes required to construct the immediate"
<gordonDrogon>
I guess that might make sense from a hardware designers point of view...
<Sofia>
gordonDrogon: Fortunately software rarely needs to encode immediates. Hardware has to decode them millions to billions of times per second. I'd rather save the area. (As a software engineer writing a RISC-V compiler.)
<gordonDrogon>
I'm currently writing a little emulator but ultimately want some 'real' hardware - even if that's FPGA..
<gordonDrogon>
and in BCPL in my case just a few more lines of code :)
<Sofia>
Why? o.o
<Sofia>
ENJOY THE CAPSLOCK MODE
<gordonDrogon>
because I have a nice little retro system and milti-tasking OS I wrote in BCPL currently running on a 65x816 system that I want to make go a little faster ... so I'm writing the RV emulator in bcpl on that system...
* Sofia
blinks
<gordonDrogon>
when I can run a bcpl program under RV emulation I'll look at real hardware, so bcpl compiled to Cintcode interpreted by RV assembler running on a virtual RV emulator written in BCPL compiled to cintcode exectuted by the '816 ...
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<jrtc27>
or you take the arm approach
<jrtc27>
nobody cares about a few extra muxes in decode
<jrtc27>
except for the kinds of cores that should just be fixed logic rather than general-purpose processors
<sorear>
not saying you're wrong but especially T32 has some interesting encodings
<jrtc27>
solution: don't try and define a single ISA that works for M-class and A-class cores
<jrtc27>
they have totally different requirements
<jrtc27>
see: the mess that is the CLIC, Zce*, etc
<jrtc27>
trying to butcher RISC-V to look like Arm-M
<jrtc27>
in what world is CAS verboten but C.PUSH/C.POP of a register set ok...
<jrtc27>
just give me my register pair CAS already...
* Sofia
likes LR/SC,
<jrtc27>
lr/sc doesn't scale as well, and is no more powerful than cas once you factor in the requirements for riscv's forward progress guarantee
<jrtc27>
including regarding the aba problem
<jrtc27>
the only thing against cas is its requirement for writing back to two registers
<jrtc27>
but we have a bunch of extensions that do that now already
<jrtc27>
albeit to adjacent even register pairs
<jrtc27>
(RV32Zdinx and the in-progress RV32P)
<jrtc27>
and Zce wants a C.POP that can pop some crazy number of registers from the stack in one instruction
<jrtc27>
so that ship sailed
<Sofia>
As for Zce, specifically the push/pop et al, I'd rather fix optimizing compilers than introduce those instructions...
<jrtc27>
yes, the approach is flawed
<jrtc27>
also the ungodly c.mva01s01 or whatever the hell it is
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<Sofia>
o.o
<jrtc27>
I hate so many things about Zce* :)
<Sofia>
How about muli?
<jrtc27>
it's a much more reasonable instruction to add, though I don't know how useful it is in practice
<jrtc27>
could be useful for array indexing
<jrtc27>
but so would reg+reg addressing...
<Sofia>
sh[123]add are good enough there IMHO
<jrtc27>
only if your element size is 2, 4 or 8 bytes
<jrtc27>
otherwise you need a bunch of them
<Sofia>
Or 3, 5 or 9
<jrtc27>
which is maybe ok, because that's what mul will do
<jrtc27>
just a bit more code
<jrtc27>
this is why I like x86 and arm, you can do the shift+add all in the load for simple cases
<jrtc27>
aarch64 that is; aarch32 has its own issues
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<Sofia>
[234589]x multipliers from just slli and sh[123]add alone. Decent little chunk of multipliers.
<jrtc27>
I'd prefer the compressed instructions went away rather than wasting 3/4 of the encoding space
<jrtc27>
they're another way in which riscv is optimised for microcontrollers not "real" computers
<Sofia>
Uhh, the compression enables much cheaper fusions for those "real computers"
<Sofia>
4 compressed instructions could be fused into a single operation to cover your addressing needs. If you're not compressing, the same 8 bytes only gives you two compression fusions.
<Sofia>
two instruction fusions*
<jrtc27>
but those two instructions could each do the work of 2 compressed instructions, because your ISA has richer instructions baked in
* Sofia
shrugs
<Sofia>
At some point you just want to write micro operations in 5-6 bits each.
<Sofia>
(Whose register arguments are implied; unless explicitly selected by other micro operations)
* Sofia
has some microarchitecture-compiler codesign ideas but doesn't intend to play with that for a while.
<Sofia>
And when I do, it won't target ASIC or even FPGA at least initially. It'd be a virtual machine targeting more obscure contexts where the cost functions can vary chaotically due to limited control.
* gordonDrogon
pops back for a moment.
<gordonDrogon>
I'm no expert in chip design but after nearly 45 years doing software and hardware my own personal feeling is that things are just too complex now. Too many gates, too many lines of code, too many things stuffed into one SoC - so that introduces complexity and designs (software & hardware) that are impossible to be bug free. But today it's just too easy to pull in some million-line 'framework' or copy & past blocks of hardware designs into an S
<gordonDrogon>
oC and hope for the best.
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<gordonDrogon>
fortunately for me, this is all mostly hobby now...
* Sofia
is no stranger to fresh slate design :)
<Sofia>
clean slate
<gordonDrogon>
I'll get into fpga's one day - but maybe then something new will have come along ...
<Sofia>
gordonDrogon: Asynchronous FPGAs are neat ;-)
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<jimwilson>
we will never be able to compete with armv7 on code size until we have load/store multiple, the question is just what form to add
<jimwilson>
c.push/c.pop have the advantage that they are drop in replacements for -msave-restore, and hence the compiler support is trivial
<jimwilson>
if you have a better suggestion, then please go ahead and make it to the code-size committee
<jrtc27>
my first thought would be it's 2021 nobody should be caring about that
<jrtc27>
my second thought would be a compressed (and uncompressed...) load/store pair would probably do a lot of heaving lifting
<jrtc27>
s/2021/2022/ even
<lagash>
jrtc27: failed already, eh? every new year I try and see how long it takes for me to make that mistake :D
<jrtc27>
the nearer it is to the start of the year the less shame there is in it :)
<jrtc27>
but, re load/store pair, they should be a heck of a lot more flexible, I bet you'd find a lot of uses for them in codegen
<jrtc27>
so whilst, yes, prologues and epilogues won't be as concise as with push/pop, you may well win out overall because they're not dedicated-purpose instructions...
<jrtc27>
but hell will freeze over before I wade into *that* committee
<jimwilson>
memory still costs money, the embedded market cares a lot about how much flash/rom/ram they have to buy when building products, so code size still matters
<jimwilson>
especially when the difference is so large, some people see a 40% code size increase when switching to RISC-V, though some of that is due to comparing embedded compilers with linux compilers, still it is over 20% even when keeping the compiler the same
<jimwilson>
load/store pair would be good
<jrtc27>
yeah, one of the few things aarch64 kept, which is telling
<jrtc27>
hm, flash is more expensive than I thought
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