sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<la_mettrie> didn't find explanation for this .LC0
<la_mettrie> for instance (gcc output): luia5,%hi(.LC0)
<la_mettrie> lui a5,%hi(.LC0)
<la_mettrie> uh, it's defined in the code itself... so it's a label inserted by the assembler program
<geertu> yep
<geertu> And what's the next instruction?
<la_mettrie> ld a5,%lo(.LC0)(a5)
<la_mettrie> (i didn't find any convincing answer for how to make 64-bit values in risc-v assembly so i'm studying gnu-as's (gcc) output)
<psydroid> is that even possible?
<psydroid> I didn't come across any when I read the RISC-V Book
<psydroid> other than the hi/lo thing
<psydroid> like on POWER
<la_mettrie> somebody made it by loading bottom twice with ordinary instructions and shifting in between...
<la_mettrie> this is how to do it in ARM64. one thing i'm curious about is if it's any less cumbersome in risc-v https://pastebin.com/raw/t7VPdghi
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<enthusi> I think you either load it from memory, or in general you can still create some
<enthusi> 'nearby' 64bit address
<enthusi> or slli and or
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<jrtc27> you can't generate 64-bit addresses via relocations
<jrtc27> you can generate addresses within a 32-bit (ish) signed offset of PC
<jrtc27> which could be a 64-bit value
<jrtc27> or you can generate addresses that fit in a 32-bit (ish) signed integer
<jrtc27> you can synthesise any constant integer you like, but that uses techniques for which there aren't relocations
<jrtc27> if you need an arbitrary 64-bit address then you need to load it from memory
<jrtc27> either via the GOT or your own constant pool (which is what the GOT basically is)
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<dh`> that seems shortsighted :-/
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<palmer> just to be clear: you can generate 64-bit addresses via relocations, just not via in-line addressing sequences
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<jrtc27> right, I was slightly unclear there
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<dh`> thcd
<dh`> oops
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