sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<ssb> dh`, it was a qemu linux-user bug in waitid()
<ssb> and it happens only on riscv32 because there it is the only wait syscall. In other targets I tested (alpha, riscv64) different code path in glibc is triggered.
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<dh`> yeah, I didn't want to know. glibc--
<dh`> :-|
<ssb> no why? no bug in glibc )
<ssb> I'd guess it would fail in the same way with other libcs
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<cousteau> Hi!
<gordonDrogon> cousteau, morning.
<cousteau> Are there plans to have a K extension ("Krypto")? Or are crypto-related instruction groups being named Zk* and Zbk* for informative purposes only, and not because the "K" is meaningful as an extension name?
<cousteau> I've noticed that Z<letter>* sub-extensions are usually related to the <Letter> extension, not sure if that's an "official" pattern...
<cousteau> e.g. the Zfinx extension is related to the F (and D) extension, the Zbc extension is related to B, etc
<dh`> ssb: because paths like that shouldn't be machine-dependent
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<gordonDrogon> hmph. emulating RV-32I BGEU on a system with a language with only signed integers is less elegant than I think it ought to be...
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<jrtc27> just add 2^31 to each?
<jrtc27> signed vs unsigned in two's complement just changes where the discontinuity is
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<gordonDrogon> yes.
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<gordonDrogon> implemneting RV-32IM, once insturction at a time ;-)
<gordonDrogon> sort of surprised at how little instructions it really needs - using a small C program to test - the C compiled to 595 instructions with -O0 and 194 instructions with -O3
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<ssb> dh`, sure that would be great. Life is different though, system call interface required to carry old and misdesigned cruft for compatibility reasons. And is not compatible itself between 32/64 bit variants of same architecture, let alone different ports.
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<la_mettrie> different sources seem to give contradicting answers to how many addressing modes risc-v has. answers have varied in range 1-4
<la_mettrie> hm, it's possible that different sources also have a bit different ideas about what addressing mode means...
<gordonDrogon> highly likely..
<la_mettrie> here on the page 29, it says four modes https://www.cse.iitk.ac.in/users/biswap/CASS18/ISA.pdf
<la_mettrie> vs. in the beginning here it says two or three modes https://www.sifive.com/blog/all-aboard-part-4-risc-v-code-models
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<palmer> IMO that's just a terminology difference, trying to count instruction formats and addressing modes ends up pretty subjective
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