#riscv on 2022-01-10 — irc logs at libera.irclog.whitequark.org

2021-08-01 01:31 sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv

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05:07 <Bluefoxicy> holy cats

05:07 <Bluefoxicy> https://i.imgur.com/z9lwbwp.png

05:07 <Bluefoxicy> it friggin works

05:08 <Bluefoxicy> I had to add like 9 more gates because I misunderstood the math a little, but none of them are on the critical path

05:10 <Bluefoxicy> :| it's weird sitting on something AMD and Intel haven't been able to figure out in the past 60 years

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06:29 <Sofia> Bluefoxicy: You believe you have a faster division implementation than AMD and Intel?

06:43 <Bluefoxicy> Current state of the art is SRT division using a look-up table

06:43 <Bluefoxicy> I have a trivial circuit that can generate any cell in the look-up table \o/

06:44 <Bluefoxicy> i.e. I'm using what is in current (2017 and more recent) research considered to be a division circuit requiring a ROM and an address decoder, for which there is ongoing research into doing things to get around the look-up table being so damned slow

06:44 <Bluefoxicy> and not doing any of that

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07:16 <Sofia> Interesting algorithm for division.

07:17 <Bluefoxicy> it's from like 1950-ish

07:18 <Bluefoxicy> what's weird is everyone had the specs for the look-up tables, but one of the big advances made around 1970 was a foldable look-up table so you could store it in half the PLA space

07:19 <Bluefoxicy> literally just draw a picture of the table, draw the 1/3 D and 2/3 D and 8/3 D lines and whatnot, and color in the boxes until you have something logical, it's not hard

07:21 <Bluefoxicy> what bugs me is IEEE754 doesn't seem to explain how it wants division done, and while you get 2 digits of the quotient each iteration, you really need to check your internal precision

07:22 <Bluefoxicy> otoh that may be because Lukas had hard-coded 52 bits of internal precision in his application

07:22 <Bluefoxicy> I started getting incorrect results at 27 digits of precision—base-4 digits, 54 binary digits.

07:24 <Sofia> I thought you were sleeping <_<

07:24 <Bluefoxicy> i should do that

07:24 <Bluefoxicy> my cat is whining at me because he wants me to get in bed so he can use me as a pillow :|

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07:26 <Sofia> Cute

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07:51 <solrize> https://stackoverflow.com/questions/50966676/why-do-arm-chips-have-an-instruction-with-javascript-in-the-name-fjcvtzs haha

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08:54 <Sofia> solrize: Hmmmm.. https://godbolt.org/z/dMf7TWhMr

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08:56 <Sofia> Under clang, the result is so undefined it inherits uninitialized register values?

08:58 <gordonDrogon> by my newbie+naive understanding; looks like it.

08:58 <gordonDrogon> someone pointed out compiler explorer to me just yesterday too. I think he was trying to persuade me to not use ASM for my project.

09:00 <Sofia> gordonDrogon: What were you using assembly for?

09:00 <gordonDrogon> I still am using asm - it's for a freestanding project which is a small bytecode interpreter/vm thingy.

09:02 <Sofia> I mean, you wrote assembly for what?

09:02 <Sofia> Vs. writing code in any higher level language

09:03 <gordonDrogon> the project is currently on the 65815 (16-bit version of the 6502 - ish) looking to move it to risc-v.

09:03 <gordonDrogon> the bytecode is what BCPL compiles into.

09:04 <gordonDrogon> so I currently have a little retro style OS and utilities all in BCPL and it runs well, if a little slow on the '816 system, so looking at something a little faster.

09:05 <gordonDrogon> I could run it all under Linux on my desktop where I have a C version of the bytecode/vm but that's too easy..

09:05 <Sofia> solrize: I forgot to check clang for x86-64. It shares the undefined uninitialized result. Odd. https://godbolt.org/z/8MGfE3q86

09:06 <Sofia> At least Rust defines the semantic. But it seems to add additional code for the casting.

09:06 <Sofia> s/seems/

09:07 <Sofia> s/seems to add/adds/

09:07 <gordonDrogon> hence my recent quest for a small RV system that's in-between 32KB microcontroller and not 4GB Linux. ESP32-C3 or FPGA...

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09:08 <Sofia> Good luck gordonDrogon

09:08 * Sofia thought your name ended in Dragon, just noticed now it does not.

09:09 <gordonDrogon> thanks. I've written most of an RV emulator in BCPL and am testing out snippets of the bytecode in that - fun but slowish.

09:10 <gordonDrogon> this person: https://github.com/ultraembedded seems to have a goof fpga solution though - I'll be investigating all that soon too.

09:10 <gordonDrogon> *good

09:10 <solrize> i don't recognize that number sofia

09:10 <gordonDrogon> Sofia, yea, long story, anagram of gordon :)

09:11 <gordonDrogon> a name I picked in 1992 for a MUD I wrote & ran; The Land of Drogon ... those were the days!

09:11 <solrize> it's slightly larger than 2**32

09:11 <gordonDrogon> doggie walk time - back later...

09:12 <Sofia> solrize: It was a snippet from stackoverflow.

09:12 <Sofia> Which was different to your link.

09:12 <Sofia> https://stackoverflow.com/questions/66279679/casting-float-to-int-with-wrap-around-on-aarch64-arm64

09:13 <Sofia> One hop away from your link rather.

09:13 <solrize> oh

09:14 <dh`> oh ffs godbolt gives a blank page in my browser

09:14 <Sofia> Fun..

09:15 <Sofia> dh`:

09:15 <Sofia> #include <cstdint>

09:15 <Sofia> uint32_t cast(float value) { return uint32_t(value); }

09:15 <Sofia> uint32_t f() { return cast(4294967808.); }

09:15 <Sofia> uint32_t g() { return cast(429496780.); }

09:17 <Sofia> dh`: GCC sets f = -1, g = 429496768. Clang aggrees for g, but leaves f undefined by returning straight away without even initializing the a0 register to a constant.

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09:18 <dh`> that seems thoroughly wrong

09:18 <Sofia> The float in f is too large to fit in u32, while g somehow gets divided by 2.

09:18 <Sofia> er, not 2, 10.

09:19 <dh`> though I suppose casting out-of-range values from float and double isn't defined

09:19 <Sofia> That is the point, but it is still unexpected to see the result be this degree of undefined...

09:20 <dh`> that's the problem with the current attitude towards UB

09:21 <dh`> it would be more helpful to just call abort(), but no...

09:21 <Sofia> Or just trap.

09:22 <dh`> let me guess, neither prints a diagnostic

09:22 <Sofia> Correct.

09:22 <Sofia> Though I'll admit I didn't add -Wall or even check for that

09:22 <Sofia> Adding -Wall did not yield any warning.

09:23 <Sofia> Nor with -Wpedantic.

09:23 <dh`> ok, I got godbolt to run, and now I can't paste from it

09:23 <Sofia> Wonderful.

09:23 <dh`> I swear, the world is made of regressions this decade

09:24 <Sofia> Shall we start from scratch?

09:24 <dh`> godbolt is a pretty neat toy but browsers should be burned down

09:27 <Sofia> Yes.

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09:45 <Sofia> dh`: #llvm on oftc. -> add -fno-strict-float-cast-overflow to define the semantic.

09:48 <The_Decryptor> For LLVM you can pass "-emit-llvm" to get it to emit bytecode instead of assembly, it's "optimising" out f() at that point

09:48 <muurkha> ugh

09:51 <Sofia> The_Decryptor: But that doesn't work if it is a library...

09:51 <Sofia> I.e. something links against it and calls the function.

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10:09 <The_Decryptor> I don't think it'd happen with a library, unless you're doing LTO

10:09 <The_Decryptor> With optimisations off it produces a value and calls the function

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10:09 <muurkha> but what will the function return?

10:10 <The_Decryptor> Optimisations will enable inlining, and it'll basically see an invalid value is being passed to something that can never produce a valid output

10:10 <muurkha> if it doesn't even initialize a0 it'll return whatever was previously in a0

10:10 <The_Decryptor> Yeah, that's how LLVM handles "poison" values

10:11 <The_Decryptor> A random but fixed value, so it just uses whatever is in a register at the time

10:12 <Sofia> I really don't like that..

10:12 <The_Decryptor> Same thing happens if you give it a NaN, in clang at least

10:14 <muurkha> computers were a mistake

10:14 <muurkha> burn it all down

10:15 <Sofia> muurkha: Wait for the RISC-V cores to be ready to replace those burned x86 and arm machines first.

10:15 <muurkha> won't matter if they're running software compiled with llvm

10:16 <Sofia> So use different compilers.

10:16 <enthusi> gordonDrogon: Hah, that sounds pretty similar to what I am currently doing

10:16 <enthusi> a simple minimal OS in asm for fun

10:17 <enthusi> but most likely way simpler than yours/anyones idea of an OS :)

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10:22 <gordonDrogon> enthusi, My OS is in BCPL, but I need the bytecode interpreter for the code the BCPL compiler produces... So I have a slight advantage :)

10:24 <Sofia> enthusi: I like simple. Any links?

10:25 <la_mettrie> my RISC-V ISA manuals (unprivileged from 2019, privileged from 2021) do not mention global pointer at all. have they been dropped??

10:25 <la_mettrie> nor thread pointer

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10:39 <Sofia> Huh.

10:39 <Sofia> The handbook vanished

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10:40 <Sofia> la_mettrie: Bibliography [1] RISC-V Assembly Programmer’s Manual. https://github.com/riscv/riscv-asm-manual.

10:40 <Sofia> https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md

10:43 <la_mettrie> those seem to contain thread pointer & global pointer only in a part which is from 2017 (older than official (?) manuals that do not contain them). so it seems they are dropped?

10:46 <Sofia> la_mettrie: I don't know what would be the dropped detail. The RISC-V C calling convention defines their use. It is primarily useful for linking code together, especially with C code, across boundaries where the optimizer might not have visibility (perhaps because a library is dynamically loaded.)

10:47 <Sofia> The compressed instructions extension assumes the convention is followed to optimize its encoding, thus the "stack pointer" and "return address" registers are at least more set. Still by convention and convenience, but you're still free to use whatever registers you like.

10:50 <la_mettrie> as i said, since the latest ISA manuals don't mention thread & global pointers, i'd like to get it confirmed are they dropped or not

10:51 <la_mettrie> (yes, they are just alternative names for general registers. but anyway...)

10:51 <enthusi> Sofia: nothing of the current

10:51 <enthusi> Sofia: 'project' yet but a couple of things that are related: https://github.com/enthusi/mandelbrot_riscv_assembler

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11:13 <Sofia> la_mettrie: The only mention of "thread pointer" and "global pointer" are exactly in that handbook. The only difference I see is the handbook being moved out of volume I. Volume I still references it. https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf

11:14 <Sofia> I do not interpret this as dropped.

11:16 <la_mettrie> okay, the problem was simply that okular's find feature didn't find it from that table

11:16 <la_mettrie> (okular = pdf reader)

11:29 <Sofia> la_mettrie: Oh, I thought you were comparing official 2019 with master, for which the latter does not mention these directly as the handbook has been split out.

11:30 <Sofia> I suspect the split is due to the platform and profile specs.

11:30 <Sofia> https://github.com/riscv/riscv-profiles/blob/master/profiles.adoc

11:31 <Sofia> https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc

11:31 <Sofia> https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc#software-and-abis

11:31 <Sofia> >

11:31 <Sofia> All RISC-V software components must comply with the RISC-V procedure call standard [12].

11:32 <Sofia> [12] RISC-V Procedure call standard, Version: draft-20210810

11:32 <Sofia> https://github.com/riscv/riscv-elf-psabi-doc

11:32 <Sofia> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc

11:32 <Sofia> la_mettrie: As active as I think you can get it. :)

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12:01 <gordonDrogon> enthusi, re. mandelbrot - nice to see some other hand-written assembler for RV - thanks.

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14:49 <enthusi> gordonDrogon: Thanks for the feedback :) there is also some small lz4 decoder for rv32 on my github which might actually be useful

14:50 <gordonDrogon> enthusi, my plan is to get my bytecode thing going then I can jump in with BCPL ...

14:56 <enthusi> yes, BCPL seems ideal for that. Wasnt that even the main purpose? To set foot onto new architectures? ):

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15:25 <gordonDrogon> not sure, but it was designed with portability in-mind way back in the late 60's.

15:26 <gordonDrogon> with the compiler outputing code for some virtual machine, so all you needed to do was write the interpreter for the code to bootstrap bcpl...

15:26 <gordonDrogon> I'm considering BPCL a RISC version of C :-)

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15:49 <gaude> anyone here using riscv and xip?

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16:14 <enthusi> gordonDrogon: well, it was BCPL -> B -> C, wasnt it?

16:18 <gordonDrogon> enthusi, yep...

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17:26 * geertu has fond memories of BPTR and BSTR

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19:06 <gordonDrogon> I don't recognise those, but I didn't get into BCPL until about 1983...

19:07 * gordonDrogon guesses a byte pointer and string..

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