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<nortti>
apropos the vax discussion last evening, why does it use that kind of paging anyways? is the 512 byte page size to align with the sector sizes on disk media?
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<netbsduser>
nortti: yes, exactly that
<netbsduser>
they were pioneering with respect to virtual memory and were concerned that a page size not equal to the physical block size of disks would be harmful to that
<nortti>
and I guess linear page tables were for simplicity of implementation?
<netbsduser>
i think it would´ve been specifically for the simplicity of implementing pageable user page tables
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<zid>
hello feet
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<heat>
gello
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<mcrod>
hi
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<Ermine>
heat: how do you feel yourself
<heat>
i feel like ass
<heat>
at least i feel better than yesterday morning but that's a low point innit
<heat>
still have issues eating but im kinda hungry
<heat>
dreamed about eating kitkats ngl best dream ever
<Ermine>
that sucks
<heat>
it does but At Least Im Not Puking
<heat>
And Im Watching The Footy
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<gog>
HI I'M SAD
* kof123
.oO( innit init system )
<gog>
and i'm doing capslock by accident
<kof123>
why are you sad gog?
<Cindy>
gog: hi sad i'm sad
* ChavGPT
hugs gog
<ChavGPT>
there there
<heat>
gog: SAD is actually a type of company here in portugal
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<Ermine>
gog: may I pet you
<gog>
hi
<gog>
yes
<gog>
probably nothing idk
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<x8dcc>
is it a good idea to store the FPU/SSE state with fxsave when initializing multitasking and then using that as base when creating new tasks?
<heat>
erm
<heat>
maybe?
<heat>
so, it's kinda useless
<heat>
there's only 1/2 words of state you need to set when initializing an FPU context, and those can be set directly in the xsave map easily
<bslsk05>
github.com: Onyx/kernel/arch/x86_64/fpu.cpp at master · heatd/Onyx · GitHub
<heat>
if everything else in the FPU area is zeroed you have an EZPZ FPU SQZ
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<x8dcc>
that's helpful, I will do that instead
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<x8dcc>
thank you :)
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<heat>
np
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<geist>
yah i think they explicitly set it up so that all zeros is the default. at some point i decoded how all of that compressed xsave stuff works, but its a little wonky
<geist>
but i think some of the wonkiness is because of the zero-is-default-state mechanic
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<geist>
nortti, netbsduser: also re: the vax linear paging, it was an era when a full 32bit address space was huuuuuge, generally well beyond the size of the largest machine
<geist>
so the ability to restrict the user space with a length field and not use up a large page table probably seemed like a good idea
<geist>
though i guess the radix tree style page table also accomplishes fairly the same thing
<geist>
as far as i know even in the later vaxen, when the initial 29 bit physical address space was startig to be a problem they still used the linear map
<geist>
seems like the kernel aspace would start getting pretty cramped with page tables by then
<nortti>
how big is a page table entry on VAX?
<geist>
4 bytes, fairly standard set of fields by modern standards
<geist>
but in initial designs 29 bits was the max physical size, the real virtual space is chopped up in a few weird ways, though not weird if you've worked with avr32, mips, or sh-4. fairly standard hard chopping of the whole aspace into user, identity map, kernel, etc
<geist>
only thing in the page table entries thats kinda neat is it has the ring level in it, so it's more powerful than 386's mapping of rings to user/supervisor. you can set which ring the page becomes accessible in
<samis>
that's why VMS has a number of rings and unlike x86 actually uses them
<samis>
right?
<geist>
yeah. i think the other way of looking at it is vax had a number of rings that it intrinsically used (or VMS did at least), and intel copied that with 286 but was never really used that much
<nortti>
hm, OS/2 used rings for device drivers on 80286, right? what did it do for 386?
<geist>
i think OS/2 was the main user of rings, yeah
<geist>
i booted OS/2 on qemu one time and broke into it a few times to see what the state of the cpu was and it was definitely using ring 2 a lot
<geist>
how that really gets you much protection since the paging scheme only gives you 2 i dunno
<geist>
but i suspect they split the kernel up into core kernel and then some sort of supervisor level drivers/etc code so maybe there was a bit of advantage there
<geist>
you can learn quite a bit by booting something like dos with emm386.sys or win 3.1 on qemu and just breaking into it and see how it's using the GDT and page tables
<geist>
pretty educational
<zid>
or forgeddaboutit
<zid>
it's 2023 baby, 64bit virtual address spaces for everyone
<nortti>
does any CPU architecture actually give 64 bits of virtual address space?
<zid>
Not sure actually
<nortti>
afaict 39, 48, and 56 seem like the common values
<zid>
"48 is the best I can do" --CPU makers
<geist>
fairly sure ia64 does
<nortti>
oh, interesting
<nortti>
does it just do a deeper radix tree?
<geist>
iirc it chops the full virtual space into 8 separate zones, each zone has it's own paging structure
<geist>
so you can use that however you want, 2:2, 7:1, 1:6:1, etc
<geist>
so each paging structure deals with 2^61 of it
<geist>
but basically that means you have up to 8 things to context switch
<geist>
depending on how you choose to use it
<geist>
and no ia64 does not use a radix tree at all, it's a very very different design
<geist>
closer to POWER/PPC but it has two modes that you can choose per structure iirc
<geist>
basically part of the control register set up
<geist>
long vs short page table entries, etc. but one of the modes looks a bit like vax in the sense that it's a large linear page table that lives in virtual space
<geist>
iirc that's the short page table entry mode, the long mode is i think closer to POWER in that it's a huge hash table
<geist>
i think those page table entries are 16 bytes long, iirc
<geist>
been a while, actually heat grokked it all at once
<geist>
ITAAAAANIUM
<heat>
ITAAAAAAAAAAAAAANIUUUUUUUUUUUUUUUUUUUUM
<heat>
nortti: don't forget 36 btw, afaik 36 is also pretty common
<heat>
hm sorry 36 bits seemsto be common for a physical address
<heat>
also it's 57
<heat>
you go 48 -> 57 cuz of 9 extra bits
<heat>
and on ARM, 49 -> 58
<heat>
IF they have 58-bit addressing, which I don't think they do?
<childlikempress>
I thought arm had a 52-bit thing?
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<heat>
(ARM has an extra bit because it has two radix trees instead of one)
<heat>
idk, probably
<heat>
i don't remember all the details, i just did 48-bit
<heat>
*49
<netbsduser>
interestingly the VMS port to Alpha was done by implementing a vax macro assembly 2 alpha compiler
<heat>
good
<heat>
what a great solution
<heat>
up yours dave cutler
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<childlikempress>
remember #define rax x0 from apple or whatever it was
<heat>
with all the registers arm has you could even define-emulate MMX
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<heat>
imagine the possibilities
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<childlikempress>
ooh I just realised something
<childlikempress>
the x87 stack has 8 elements
<childlikempress>
so you can shove the entire thing into an avx512 register and emulate the stack ops with shuffles
<gog>
RYYYYYZEN
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<heat>
thank you childlikempress, very cool!
<x8dcc>
heat: I am setting [edx + fpu_data.mxcsr] (allocated+0x18) to dword 0b0001111110000000 (0x1F80) but now I am getting a x87 floating point exception :(
<heat>
then something else is wrong
<heat>
because That Just Works(tm)
<x8dcc>
rest of the 512 bytes are zeros
<x8dcc>
the exception occurs on a fstp instruction
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<kof123>
one small step for x87, one giant leap towards pages in registers
<heat>
wait
<heat>
why the fuck do you have x87 instructions?
<x8dcc>
not sure
<childlikempress>
kof123: the avx512 state is 2kb
<childlikempress>
and an avx512 instruction has a 2-bit register size header whose meanings are: 16 bytes, 32 bytes, 64 bytes, unassigned
<childlikempress>
SO they could double the register size still, and literally store a page in registers
<childlikempress>
HTH.HAND
<heat>
oh, 32-bit codegen uses x87 by default
<heat>
ew
<childlikempress>
-msse or sth
<childlikempress>
or just do 64 bit
<heat>
x8dcc: did you configure the FPU properly
<heat>
where are you catching this exception? hopefully not the kernel?
<x8dcc>
I think I configured fpu properly, but I usually my errors happen because I think I did something right when I didn't
<x8dcc>
childlikempress: I use -msse and -msse2 currently
<heat>
where
<heat>
what is crashing?
<x8dcc>
my %f format for printf
<x8dcc>
and I only have kernel, I don't have userspace or anything
<heat>
oh god
<heat>
don't
<x8dcc>
I haven't touched the project in some months
<heat>
rm -rf %f handling
<heat>
and then rm -rf -msse -msse2 from your kernel's CFLAGS
<childlikempress>
don't do fp in kernel
<x8dcc>
well I don't have anything else haha
<zid>
afaik in linux to do fp you have to call a special lock + init function, do your shit, then release?
<zid>
and it's only used by like, the crypto api
<x8dcc>
childlikempress: why is it bad to use fp in kernel?
<childlikempress>
I think there's a flag you can pass to tell the compiler to refuse to emit any kind of fp code? Or do a softfp even when the hardware supports hardfp? (Which amounts to the same thing--don't link in the softfp lib, so you'll get a link error if you try to use it)
<zid>
-mgeneral-regs-only for life
<zid>
Then never bother to make a libgcc, so that if you ever need one it fails to link
<childlikempress>
yeah that was it
<childlikempress>
no why what's wrong with libgcc
<zid>
it'll have the float cast etc code in it
<childlikempress>
oh
<heat>
x8dcc: floating point sucks, and you'll need to consistently save/restore FPU regs after kernel entries and exits
<heat>
which is expensive
<x8dcc>
well that's a bit depressing
<heat>
why?
<x8dcc>
because I spent a lot of time trying to fix stuff related to this for nothing
<x8dcc>
but whatever
<zid>
fairly sure you were told not to last time too
<x8dcc>
don't remember, but you might be right
<x8dcc>
learned in the process so I don't mind that much
<childlikempress>
I mean tbf it _should_ work, since you're not actually doing any context switching (I presume)