_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<MoeIcenowy> --with-pcie fails on Vivado 2022.2 for STLV7325 board
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<Guest9> Hi, I would like to know if there is any documentation to understand how to generate RTL for the LiteDRAM. The current github page shows "Export Your Core SoC To Verilog" as a TODO.
<_florent_> Guest9: LiteDRAM has a specific generator for this: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py
<_florent_> Guest9: you can find some configuration files here: https://github.com/enjoy-digital/litedram/tree/master/examples
<_florent_> Guest9: Some examples of re-integration:
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