13:05 <kanunay> I'm working on a standalone litepcie core but cannot seem to figure out how to get LitePCIeWishboneMaster to do what I want. I have a wishbone DMA bus, that when I inspect the generated verilog, seems to have nothing connected to it.

14:58 <_florent_> bentomo: You can find an example of simple generator here: https://github.com/enjoy-digital/litex_rp2040_pmod_test/blob/master/spibone_gen.py

14:58 <_florent_> bentomo: It's use to generate a SPI <-> Wishbone/AXI-Lite verilog core to be re-integrated in a regular flow or in another top level LiteX SoC

15:02 <_florent_> kanunay: are you using the LitePCIe generator?: https://github.com/enjoy-digital/litepcie/blob/master/litepcie/gen.py

15:03 <_florent_> kanunay: you could generate an example core for the AC701 (for example) with: litepcie_gen ac701.yml

15:04 <_florent_> kanunay: you can also find an example where the standalone core is re-integrated here: https://github.com/enjoy-digital/litepcie/blob/master/bench/acorn.py#L49-L142

15:05 <_florent_> kanunay: if you are re-integrating the core in a traditionnal flow, you could do something similar

16:34 <kanunay> Thanks for the links, after some corrections I seem to have it working now.

17:21 <bentomo> _florent_ Thanks as always! Now that I'm getting some more time with the various environments, my interpretation is amaranth seems like a great low level alternative to S/V/HDL and it includes a simulator. And litex is a larger, but more complex environment. It's not impossible to intermix them but it takes extra work.

17:22 <bentomo> And they both use Yosys under the covers still so it's not as though the framework is really different per say.

17:22 <bentomo> ls

17:23 <bentomo> Whoops, that "ls" was meant for my terminal, sorry XD

18:09 <bentomo> _florent_ THE SPI-BONE DOCUMENTATION IS BEAUTIFUL! Just calling generate_docs on the core and running sphinx was super easy and gives GREAT looking specs! This is such a good framework!