<_florent_>
sensille: if you are not using add_ethernet, have a look at how the clock domain renaming is done in it to see how to apply it to LiteEthMAC
<_florent_>
(but that's something that should be improved)
<sensille>
i spent quite some time there yesterday reading the code. i think phy_cd does not do the trick, it only applies to bus width != 32. but anyway, i also found that the device has not enough resources to handle an additional interface just for debugging purposes
<_florent_>
ah OK... you could eventually add a second UART + UARTBone if that's possible/convenient on your system.
<sensille>
i tried uartbone, but that's too slow on my system, mainly because the usb uart dongle add to much latency
<sensille>
although echo 1 > /sys/bus/usb-serial/devices/ttyUSB0/latency_timer improved it a lot
<sensille>
i now have a somewhat working dev environment. my current problem ist that i can't increase integrated_main_ram_size above 0x1000. synthesis works, but the BIOS-ram-test fails
<_florent_>
sensille: strange, which FPGA board are you using?
<sensille>
linsn_rv901t, spartan6
<_florent_>
OK, strange. And what's the test behavior? do you only get errors for addr >= 0x1000 or even for < 0x1000?
<sensille>
even for the base 0x40000000. write does nothing, read gives data from an address in the middle of the ROM. like offset 7758 in ROM
<sensille>
even stranger, 40000004 give the next word from rom
<sensille>
address decoding can't be that wrong
<_florent_>
hmm, can your provide the generated software/include/generated/mem.h?