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<sensille>
interesting. I built my soc with uartbone + crossover and tried to access it via wishbone-tool -s terminal. it somehow works, but needs minutes to print the welcome message
<sensille>
building wishbone-tool from source does not fix it
<sensille>
memory access via wishbone-tool is quick
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<sensille>
it turned out to be a signal quality issue: i use this china ft232rl board, very simple
<sensille>
they managed to even screw that up: they left vccio floating. it somehow works, but not really
<sensille>
results in crazy crosstalk between rx and tx