_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
Degi has quit [Ping timeout: 240 seconds]
Degi has joined #litex
cr1901 has quit [Remote host closed the connection]
cr1901 has joined #litex
cr1901 has quit [Remote host closed the connection]
cr1901 has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
nickoe has joined #litex
<nickoe> Hello. How can I select a signal from the platform as the clock signal with add_clocker?   i.e:
<nickoe> io_in = platform.request_all("io_in")
<nickoe> sim_config.add_clocker("io_in0[0]", freq_hz=sys_clk_freq)
<nickoe> This gives me a segfault:
<nickoe> run_sim.sh: line 1: 116 Segmentation fault (core dumped) obj_dir/Vsim
nickoe has quit [Quit: Client closed]
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
DoubleJ has joined #litex
zjason`` has joined #litex
zjason` has quit [Ping timeout: 268 seconds]