#litex on 2022-11-10 — irc logs at libera.irclog.whitequark.org

2021-05-24 10:26 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex

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04:40 <jersey99> _florent_FYI, I figured out simulating designs in VHDL. For some reason I expected migen to deliver this. And going the litex_sim route just works. Thanks!

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