00:21 <mithro> Have people here seen the work CarlFK has been doing on my behalf to enable a whole bunch of Digilent Arty A7 boards be available on the web? --> https://frontend.ps1.fpgas.mithis.com/

08:13 <_florent_> Hi mithro, that's nice yes. Is it for regression testing or to give access to developers?

08:13 <_florent_> I'm planning to put more efforts on CI with hardware in early 2023

17:56 <mithro> _florent_: I was hoping it could be used for both

17:57 <mithro> _florent_: There should eventually be ~40 FPGA boards available through this

17:58 <mithro> _florent_: The way I see it working is that you can "reserve" a board for a certain period. When the CI system wants to run a test, it requests a board out of the pool.

17:58 <mithro> CarlFK: ^

19:10 <amstan> mithro: woah! i'm always interested in new boards

19:11 <amstan> ah, it's a lab of boards, i get it

19:11 <amstan> i saw a limited count and a "reserve" and i got excited to buy something, lol

19:18 <sensille> a good reflex

19:29 <amstan> i'm still looking for some kind of cute board i can use to connect over thunderbolt only to my laptop so i can do portable fpga deving with litex

19:33 <sensille> not thunderbolt, but cute: https://www.crowdsupply.com/rhs-research/picoevb

19:33 <tpb> Title: PicoEVB | Crowd Supply (at www.crowdsupply.com)

20:06 <CarlFK> Can someone grind though the steps to make an LED blink on one of the arty boards?

20:41 <jersey99> _florent_When I am using Memory in simulation, with a read port in the usual "sys" clock domain, the memory_emit_verilog (in gen/fhdl/memory.py), seems to throw an error saying it can't find ClockSignal. The rest of the code seems to work with add_clocker, except Memory. Have you tried this before? Is it because Memory is a special and for some

20:41 <jersey99> reason the clock domain information isn't propagating to the code generator?

20:42 <jersey99> btw, as you can guess, this simulation is via Litex verilator, not Migen

20:57 <thiskappaisgrey> Hi, we are students at UCSB, and are trying to get OpenPiton (https://github.com/PrincetonUniversity/openpiton ) to run on litex. We managed to build it and got some of the bootloader code working but it doesn't print anything. We think it's related to the isr.c code but we aren't sure how it works. Can someone please explain? Thank you.

21:00 <thiskappaisgrey> Also, the discord on the readme is expired..

21:07 <thiskappaisgrey> sorry, I have to go.. I'll just ask again later.

21:30 <amstan> sensille: maybe with an enclosure

21:30 <amstan> though i was warned against enclosures before

22:14 <sensille> amstan: why enclosure? it's just meant to be put into the laptop, or what do you mean?

22:15 <amstan> i don't have room to put it inside my laptop, but i have plenty of type c thunderbolt ports

22:15 <amstan> https://www.amazon.com/Thunderbolt-Certified-Tool-Free-Enclosure-EC-T3NS/dp/B08FT59SB6