_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> kanunay: If you are using custom code, I would probably need to have a look to be able to help
<_florent_> somlo: congrats!
<_florent_> hcab14: the behavior is the following for now: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/frontend/stream.py#L38
<_florent_> hcab14: we could switch to a PacketFIFO in the future, but for now it "Sends FIFO contents when we have a full-packet or when FIFO is full."
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<shoragan> somlo, what was the issue in the liteuart driver?
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<hcab14> _florent_: thanks for your reply. In https://github.com/enjoy-digital/liteeth/blob/master/liteeth/frontend/stream.py#L39 `fifo.source.last` is used but this always points to the beginning of the FIFO, so one can detect the end tag only in the "SEND" FSM state when the FIFO is read out. Does this make sense?
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