09:25 <Yanan> Hi everyone, is there any document on how to implement a new PHY for litedram? I am planing to add support for efinix FPGAs.

14:35 <sensille> what would be a good starting point for a riscv on a small fpga with ethernet? it has SDRAM, but is probably not needed

15:15 <sensille> hm, based on SoCCore it automatically builds a ROM of 24k, which is a lot for the small chip. maybe i can add the SDRAM, copy from spi flash on startup and run from SDRAM

15:19 <sensille> maybe icebreaker-fpga is a good starting point

17:30 <zyp> sensille, you mentioned having a colorlite board the other day, in which case the obvious starting point would be the example project for the colorlite board

17:31 <zyp> e.g. https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py or https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_i5.py depending on which you've got

17:33 <sensille> yeah, done that. i mean for adding a CPU

17:33 <sensille> i have the rv901t

17:35 <sensille> i managed to build a bitstream, but it doesn't ping. while with a different project (Litex-CNC) it pings. now i'm trying to find the difference in the board definition

17:36 <zyp> by «adding a CPU», do you mean in the sense of writing your own?

17:41 <sensille> no, an existing risc core. the is what i currently have, c&p'd from various sources: https://dpaste.org/4o3rn

17:41 <tpb> Title: dpaste/4o3rn (Python) (at dpaste.org)

17:44 <sensille> i should take the working (pinging) project and morph it into what i want to have in baby steps

18:46 <sensille> boils down to: when i change sys_clk from 30mhz to 50mhz it works

18:47 <sensille> maybe ... litex derives the 30 from the 25, but not exactly, and then derives the 125mhz from the inexact 30?

18:53 <sensille> no, eth_clocks0_rx is an input

19:09 <zyp> no, it's just that 30 is too slow to keep up with the ethernet stream once the data is passed over to the sys domain

19:11 <sensille> oh. so maybe some modul could check that and bail out?

19:12 <sensille> do you happen to know what the minimum is?

19:12 <zyp> a gigabit data stream is 125 MT/s at 8-bit, or 31.25 MT/s at 32-bit

19:12 <zyp> I mean, it's as simple as 1000 / 32 :)

19:13 <zyp> I'm assuming it's 32-bit, given that it works at 50 but not 30

19:14 <sensille> :)

19:15 <sensille> it's nice that litex hides everything from me, but in a case like this at least some insight could be helpful :)

19:17 <zyp> well, you could insert a litex.soc.interconnect.stream.Monitor in a stream pipeline to gain insight into how it's performing