<sensille>
very strange. when i generate a design with 0x2000 main_ram, the main ram does not work at all (data errors: 2048/2048). when i go into the generated .v and change the size to 1024, the first 1k works. when i set it to 1025, it's broken again
<sensille>
the signals look ok in litescope. write cycle looks good to me, but the next read gives the old value
<sensille>
when i reduce integrated_sram to 0x1000 main_ram works with 0x2000
<sensille>
getting closer. main_ram size must be != sram_size
<sensille>
INFO:Xst:3227 - The RAM <Mram_sram>, combined with <Mram_main_ram>, will be implemented as a BLOCK RAM, absorbing the following register(s): <sram_adr0>
<sensille>
and indeed, main_ram content is equal to sram content (which is a copy of some rom content at 0)
<sensille>
i don't see from the generated .v why ISE thinks it can get away with using only one RAM instance for both sram and main_ram