<MoeIcenowy>
_florent_: what should I do when renaming a board?
<MoeIcenowy>
e.g. should I try to keep the old name's compatibility?
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<cr1901>
My own experience is that boards get renamed w/o regard for backwards compatibility
<cr1901>
this is what happened when most (all?) boards were renamed to have a vendor prefix
* cr1901
wonders if this changed
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<cr1901>
_florent_: litex_read_verilog doesn't seem to parse "output reg" in the ports list an ignores it. I'm deeply distracted right now, so I can't file an issue. But this at least will remind me hopefully
<mewt>
Oh that reminds me, I guess I should try and gather info for the csr_data_width problem and file a proper issue there too
<mewt>
I'll get on that in a few
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<_florent_>
MoeIcenowy: we can just rename the boards yes, no need to keep old name's compatibility
<MoeIcenowy>
_florent_: the AXI upconverter of LiteX seems to be broken
<MoeIcenowy>
I tried to create an openC906 SoC with 32-bit width bus (openC906 native width is 64)
<MoeIcenowy>
and it fails with `AttributeError: 'Record' object has no attribute 'dest'`
<MoeIcenowy>
oh sorry it's a down converter in LiteX's name
<MoeIcenowy>
oops I wrongly named it because I forget CPU is master
<MoeIcenowy>
okay it seems to be similar with c24bbedb68ee72d81159ff064c3a64ffe596429a
<MoeIcenowy>
oops that upconverter seems to be just not working at all even with this build fix
<lolock>
Hello, I need a DFI compatible SDRAM PHY (without memory controller). Can I use LiteDRAM to generate an isolated PHY?
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<mewt>
Poked a bit more into litespi and I guess I see the issue -- other cores seem not to have widths hardcoded in their layouts (common.py), I guess the way is to have a function that takes something like liteeth's "dw" as a parameter to make the layout
<mewt>
I can try to do this and submit a PR to be cleaned up over the coming days I guess
<mewt>
I will try to match what liteeth does as an example