<gurki>
trabucayre: that sounds like asking for trouble :S
<gurki>
vhdl and v are quite different in a lot of tiny details
<trabucayre>
vhdl -> v is done automatically by this class
<sensille>
from what i see it uses the toolchain directly if i supports mixed designs, otherwise it invokes ghdl for the conversion
<sensille>
*it supports
<trabucayre>
yep
<trabucayre>
most of vendors tools are able to deal with mixed langage
<trabucayre>
but for yosys you have to use ghdl-plugin or recent ghdl version to convert vhdl -> verilog
<sensille>
the ghdl plugin is installed, but litex seemed to have issued the wrong command. i will try the converter module
<gurki>
trabucayre: thats beside my point. im saying "the conversion itself is a bad idea". i can see that it just calls $thing to do the actual conversion ;)
<gurki>
if your tool can deal with mixed my point is obv moot