_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> uart rx has a quite bad performance for me
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<_florent_> wild: LitePCIe only supports one BAR for now, support for multiple BARs would probably not be too complicated to add but still needs to be implemented
<_florent_> mithro: Thanks for sharing the paper!
<_florent_> sensille: We would probably need a bit more of context: If it's with bare metal software, linux, etc...
<sensille> bare metal software, for example firmware upload via BIOS/serial fails from time to time with a crc
<sensille> i've seen that the uart module does not sync on the first bit, and does no input filtering
<_florent_> We could probably improve these two points, would you like to try contributing it or submitting an issue with your ideas?
<geertu> sensille: I get much more CRC errors when connected to a USB 3.1 Gen2 port, so I moved to a USB 2.0 port.
<geertu> many more
<sensille> _florent_: i'd like to give it a go myself
<keesj> jevinskie[m]: :P
<MoeIcenowy> somlo: please note that 64-bit memory width is not about double rank memory
<MoeIcenowy> dual rank means two set of memory chips, selectable via ~CS pin
<MoeIcenowy> 64-bit memory width is a memory bus that has a total width of 64-bit, as 8*8 or 4*16
<MoeIcenowy> SODIMMs are by definition 64-bit (or 72-bit, when ECC is available)
<MoeIcenowy> even with a single-rank SODIMM it's still 64-bit bus width
<MoeIcenowy> (e.g. my STLV7325 uses a 1Rx8 SODIMM, which means single rank and 8x 8-bit memory chips
<wild> thanks for confirming that _florent_, would I be correct to assume I would need to add support in soc.py? or would it be needed within LitePCIeWishboneMaster
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<wild> I think the peice that i am missing in my understanding is how pcie_mmap gets assigned to a BAR.
<jevinskie[m]> <MoeIcenowy> "(e.g. my STLV7325 uses a 1Rx8..." <- I was going to ask if you had a board def for that and it seems you do! Cool :) let me know if you’d like any help, I have one of those boards too. https://github.com/Icenowy/litex-boards/blob/stlv7325-enh/litex_boards/targets/sitlinv_stlv7325.py
<somlo> what's the least risky way of picking up an STLV7325 board? google returns a bunch of ebay-"like" places where seemingly private parties sell what they claim to be an STLV7325; some of them appear to be in various states of "disassembly" (e.g., only bare traces where the FMC connector(s) should go, etc). Something more "corporate" looking would go a long way toward my being able to convince my boss to spring for one, vs. me having to just buy it myself
<somlo> :D
<jevinskie[m]> I’ve always bought from HPC FPGA store on aliexpress, now called SITLINV: https://m.aliexpress.com/store/5585224
<tpb> Title: SITLINV FPGA Board Store - Amazing products with exclusive discounts on AliExpress (at m.aliexpress.com)
<jevinskie[m]> I’m not sure if that’s the store of the original board designer or not. I’m pretty sure at least some of the boards they sell are designed by the owner
<sensille> do i need to add timing constraints for clocks generated by the pll?
<sensille> i don't find the constraint for cd_sys
<sensille> looks like ISE can derive them, good
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