_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> the vexriscv just stands no chance against a burst of gbit ethernet packets ...
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<_florent_> No more excuses for not writing proper documentation: https://twitter.com/enjoy_digital/status/1598230300580253696 :)
<_florent_> Just did some tests, it seems pretty accurate, even on existing documentation
<sensille> what or who is that?
<_florent_> sensille: just testing ChatGPT :)
<_florent_> This can also be useful for LiteX users to get more info on the code if documentation is not yet written
<sensille> i was missing mainly 'big picture' documentation
<sensille> it looks insane what that project can do
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<somlo> _florent_ (or anyone else who understands DDRAM): any idea on whether the xilinx vc707 could handle *4* GB of RAM? Simply adding the missing pins only goes to 2GB by default (https://github.com/litex-hub/litex-boards/pull/457)
<MoeIcenowy> somlo: I think LiteX now has only 32-bit address space?
<MoeIcenowy> somlo: BTW dual rank memory means 2 cs pins
<MoeIcenowy> some other pins are duplicated for dual rank too
<MoeIcenowy> what you do here seem to mix up things
<MoeIcenowy> double DM, DQS and DM adds up the memory width
<MoeIcenowy> double ~CS, CLK_{p,n}, CKE, ODT is for dual rank
<MoeIcenowy> and I think for using a bigger DRAM you need to change the DRAM model in litex_boards.targets.xxx
<MoeIcenowy> with the DRAM chip model that your SODIMM uses
<MoeIcenowy> (or at least one with the same timing and capacity
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<cr1901> _florent_: Call me a neo-Luddite (actually it is accurate to the extent that I execs will use these AIs to make programmers redundant), but I wouldn't use the output of those AIs verbatim
<cr1901> I fear* execs
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<_florent_> cr1901: sure, but it seems good enough to at least give a template/structure that could give some ideas to write some documentation.
<Melkhior> _florent_: it's good on good code, but I wonder if it wouldn't be the usual 'garbage in, garbage out' on bad code - the kind that actually needs documentation...
<Melkhior> In other words, I kinda wonder what it would spit out from my code :-) but 'systems at capacity'...
<somlo> MoeIcenowy: I'm not sure we're talking about the same thing. Some CPUs have dedicated memory ports (Rocket is one such example), which get connected directly to LiteDRAM
<somlo> and LiteDRAM has a native port width that depends on the actual hardware
<somlo> in the case of vc707, it's 256 for the default 1GB single-rank chip; if one wires up the "spare" connections for dual-rank, litedram goes to 512 port width, and can address 2GB
<somlo> I was wondering if (and how) the same number of pins (dual-rank) would be able to address 4GB
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<jevinskie[m]> _florent_: I have a NightFury arriving Saturday. :) Is there a minimal example/testbench for mmaping the DRAM on the fury over PCIe? Thanks :)
<jevinskie[m]> If not, I’d like to add one but I might need some hand holding for the PCIe and mmap parts
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<zyp> IIRC the cle-215 is a rebranded nitefury, so I figure the cle-215 example should work: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sqrl_acorn.py
<zyp> also, as far as I understand PCIe, you're not gonna be able to mmap the whole DRAM on the nitefury, since the maximum size of a mappable area (BAR) tends to be fairly small
<tnt> When will we get support for Resizable BAR in LitePCIe :D
<wild> has anyone done an expansion rom (not BAR) with LitePCIe?