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<fayz>
Does any one know which riscv Csrs are required to run an RTOS on fpga.
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<muurkha>
well, you probably need to have some way to do interrupt handling. but plausibly you might prefer a nonstandard one
<muurkha>
the RISC-V standard interrupt handling approach is inherently a bit slow
<muurkha>
so, possibly none of them?
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<Muddassir_Ali>
Basically, we have an rv32i design on Amaranth that needs to run RTOS for which we need to implement CSRs so we were wondering which CSRs need to be implemented?
<muurkha>
it might depend on which RTOS you want to run on it
<muurkha>
are you writing one from scratch, or are you using an existing one?
<Muddassir_Ali>
we probably use Zephyr
<Muddassir_Ali>
yes from scratch
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<muurkha>
if you're using Zephyr, you aren't writing an RTOS from scratch; Zephyr already exists
<Muddassir_Ali>
No sorry for the misconception I don't write Zephyre from scratch.
<Muddassir_Ali>
I mean I design rv32i from scratch.
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<muurkha>
aha, that makes more sense. awesome!
<muurkha>
that file seems to use mcause, mstatus, mepc, and mscratch, which is pretty much what you'd expect from the standard RISC-V interrupt handling approach I think