sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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* enyc meows and reads scrollback
<enyc> OK so lonts of discussions of specifici RiscV issues... i was trying to ask a rother more high level question please
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<enyc> What's the situatien with RiscV mini boards along the lines of Pi-Zero-2-W i.e. mini linux that can run from 5vSB type of supply? -- spotted older https://blog.adafruit.com/2022/08/05/raspberry-pi-zero-vs-risc-v-mangopi-mq-pro-piday-raspberry_pi-bretweber/
<enyc> *** but wondering if there are names/terms/... I should be looking for ?
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<Esmil> enyc: yeah, the D1 boards are slow but super cheap, and quite well supported by the upstream kernel, so not a bad choice if price is more important that speed
<Esmil> there are even ubuntu images for two of them: https://ubuntu.com/download/risc-v (Nezha and LicheeRV Dock)
<Esmil> the next step up in price and performance would be the VisionFive 2
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<courmisch> so... what's The Right Way to indent RVV assembler. Most mnemonics are larger than 7 characters wrecking havoc to the usual style
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<sorear> the examples directory in the spec uses multiple styles so *shrug*
<courmisch> clearly we need to have a bitter unconclusive flame war
<sorear> real question is "do you differentially indent lmul-sensitive and lmul-insensitive instructions"
<courmisch> why?
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<courmisch> explicit element size adds 2-3 character, but so does .vv/.vf/.vx/.vi
<courmisch> not to speak of the conversion instructions with two or 3 dots
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<sorear> i'm talking about the style used in https://github.com/riscv/riscv-v-spec/blob/master/example/strncpy.s
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<muurkha_> courmisch: arguably aligning the operand columns isn't valuable anyway: https://prog21.dadgum.com/85.html
<muurkha_> "In the manual for Eric Isaacson's A86 assembler (which I used in the early 1990s), he advises against the age-old practice of aligning assembly code into columns, like this: ... His view is that that the purpose of a column is so you can scan down it quickly, and there's no reason you'd ever want to scan down a list of unrelated operands. The practice of writing columnar code comes from ancient tools
<muurkha_> that required textual elements to begin in specific column numbers."
<muurkha_> sorear's example seems to outdent the v* instructions?
<muurkha_> I feel that it's trying to express some program structure I'm not understanding because I haven't read the RVV spec?
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<courmisch> muurkha: doesn't look like it to me. seems pretty random
<courmisch> although I have zero practical experience with the faulting first stuff
<courmisch> multimedia took SIMD into use before faulting first was a thing, so it's learnt to live without it
<muurkha> "faulting first"?
<courmisch> sorry, fault-only-first
<courmisch> memory accesses that are allowed to cross page boundaries and into unmapped address space without crashing
<courmisch> for when you don't know the length of the vector, e.g. nul-terminated strings
<sorear> I think the intent is that it separates the actual vector instructions from the bookkeeping
<sorear> they scale differently with LMUL so
<sorear> although the handling of vsetvl is inconsistent in the examples
<sorear> fault-first is useful for any kind of loop that is otherwise vectorizable except for a data-dependent "break"
<sorear> of course if you know at the application level that the entire array is valid, you can use normal loads
<sorear> so it's more useful for autovectorization and library code with some kinds of problematic interfaces
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<muurkha> this sounds like something I should read more about
<muurkha> restarting faulting instructions more easily after page fault handling was, as I understand it, one of the major impetuses for RISC in the first place
<courmisch> in spite of its name, it's definitely not the thing to start RVV with
<courmisch> I think that's more about the vstart thing
<sorear> the fault first design is somewhat unfortunate in that you can't get full throughput without speculative execution
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<courmisch> sorear: shouldn't tail-agnostic make it work relatively painlessly?
<sorear> with a memcpy-type loop, the scalar code can run ahead and keep the vector unit 100% busy, but in the strcpy loop the backedge depends on the vl readback so unless you speculate that the next read can't be issued until the current read + compares are done
<muurkha> I guess https://yarchive.net/comp/vax.html is not what I was thinking of because it doesn't talk about page fault handling at all as far as I can tell
<sorear> I don't see how tail-agnostic helps
<courmisch> if loading some elements fail, you can just put some garbage instead?
<muurkha> what's "fault-first design"? Google isn't helping
<courmisch> as long as you don't read back vl, ofc
<sorear> I saw a twitter thread a few years ago saying that restartable page faults on GPUs were a nightmare because of how many memory references you need for biwhatever texture filtering/fetches, is that it?
<muurkha> the particular discussion I was thinking of explained that the S/360 string instructions didn't pose a real problem because they were architecturally defined to be restartable and could store the necessary state for restarting in architectural registers
<muurkha> sorear: thanks!
<courmisch> the restartability comes from vstart, not ff
<courmisch> and AFAIU, you can pretend that vstart doesn't exist unless you write an OS
<muurkha> aha, I see. so on the next iteration of the loop you get a fault at the beginning of the instruction
<muurkha> I *think* this is the same behavior as the S/360 string instructions
<sorear> the VAX string instructions are also defined to store intermediate state
<courmisch> itäs the other way around. if there is a fault mid-instruction, vstart will count how far execution went
<courmisch> so you can re-execute the same instruction, starting from where the previous execution stopped
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<sorear> extra credit for "packed decimal divide" which architecturally stores restart state at -16(sp)
<muurkha> sorear: yeah, the kinds of things Mashey (?) talked about as being problematic were things like "in the middle of the instruction we update a register or a word in memory which we previously read, so a subsequent fault in the same instruction is difficult to handle"
<muurkha> because if you just re-execute the instruction, it will use the updated value and do something different
<muurkha> so it wasn't so much string instructions he was concerned with as memory-indirect instructions (which follow a pointer in memory, apparently the 68020 did this, and of course various DEC machines could follow an arbitrarily long chain of pointers in memory in microcode)
<muurkha> and pre-increment addressing modes
<muurkha> and updating multiple registers in a single instruction
<muurkha> wording like "The values of these spurious updates do not have to correspond to the values in memory at the addressed memory locations." gives me an unpleasantly spooky feeling. A *Spectral* feeling, you might say.
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<sorear> where's that from
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<enyc> Esmil: thankyou fro thoughts! in thisn case half the puzzle is: would like something that is small enough to go inside 2.5" drivebay snetup
<enyc> like the pi-zero-2-w ........
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