sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<courmisch> drewfustini: me too, but I have a feeling it'll be yet another bit of electronic waste before long
<courmisch> what with only 512 MiB of RAM
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<unlord> does anyone know why rdtime always returns 0
<unlord> is that right?
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<geist> unlord: depends on the hardware you're on, but most of them trap to machine mode as an undefined instruction
<geist> and then opensbi/etc should fill it in
<geist> if they dont, then you'll probably get a zero. that's the default that opensbi puts in the target register if it's otherwise not providing time services
<geist> that being said if the isa features string from device tree/etc doesn't list Zinctr then i'm not sure it's 'supposed to'
<geist> but i'm not entirely clear on that
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<unlord> hmm, no zicntr but I do have a zihpm
<muurkha> Zihtfp
<dh`> Zihttps
* muurkha cowers in terror
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