sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<pabs3> anyone know what the status of Linux kernel mainline for vendors other than SiFive is?
<pabs3> if there are none other than SiFive, this makes mainline-only distro ports to riscv64 much less viable
<smaeul> C9xx-based chips (D1, TH1520, SG2042, etc.) and JH7110 are reasonably well supported
<muurkha> yeah, probably the main reason SiFive has had such a hard time getting funding is that they're not keeping ahead of folks like T-Head and Allwinner
<muurkha> which is arguably sort of unfair, since they were badly handicapped by being located in the USA, but VC isn't about fairness, it's about making lots of money
<muurkha> trying to do hardware in the US today is like trying to do it in Britain in the 01980s: the supply chains just aren't there. though ARM made out all right ;)
<muurkha> the JH7110 is mostly a SiFive design
<muurkha> just, made in Shanghai. Like VLSI and DEC made ARM's chips in the USA
<smaeul> eh, not really. the core complex is a SiFive design, but not the rest of the peripherals in the SoC
<muurkha> I guess that's a pretty important difference from how VLSI made the ARM3
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<pabs3> how about boards or full systems?
<muurkha> sure, you can design and even build boards elsewhere, lots of companies do
<pabs3> I mean, are there any boards or full systems with mainline Linux support other than SiFive :)
<heat> is the visionfive upstream yet?
<pabs3> timers, PMW, PCIe, display/camera stuff missing
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<gurki> so pretty much most peripherals :/
<gurki> these are the hard part
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<conchuod> im not sure that'd i'd put the d1 and jh7110 in the same category as the th1520 or sg2042 (yet at least)
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<geertu> conchuod: mpfs? ;-)
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<suqdiq> muurkha u think is that why sifive is going under the knife now ?
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<suqdiq> Sifive who just layed off a bunch of engineers
<suqdiq> :(
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<gurki> thats ... not a good sign
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<conchuod> geertu: I'm used to mpfs being overlooked in all conversations about riscv socs.
<palmer> that still kind of pisses me off, though, as it's the only actual production chip ;)
* conchuod shrugs
<conchuod> it's also aimed at a vastly different sector to the d1s or jh7110s of the world
<muurkha> I thought WD and family had shipped over a billion production RISC-V SoCs?
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<geertu> muurkha: ... that can run Linux
<geertu> (of course not counting anything that emulates a Linux system, like e.g. an Arduino ;-)
<geertu> palmer: RZ/Five is in production, too, AFAIK
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<muurkha> geertu: aha, yes, that's a very significant qualification that does indeed exclude the vast majority of RISC-V systems!
<muurkha> palmer: is that what you meant?
<muurkha> also I realize I should offer deepest condolences to everyone here who's involved in SiFive :(
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<suqdiq> probably related
<palmer> geertu: sweet! I thought it was just sampling, but looks pretty production from what I'm seeing
<geertu> palmer: Except for the incompatibility with standard Linux distros...
<geertu> So you need to use a patched toolchain and e.g. buildroot
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<clemens3> could it be that sifive got axed by big capital because of the US attack on risc-v in da china battle?
<clemens3> otherwise big daddy should make sure US is forefront in risc-v tech
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<muurkha> I think they'd been failing to get investment for many months, maybe years
<muurkha> hmm, CrunchBase used to be CC-licensed, but seems like now it's not even publicly available: https://www.crunchbase.com/organization/sifive
<muurkha> but https://www.crunchbase.com/funding_round/sifive-series-f--ff6938b2 lists a Series F investment round in March of last year
<muurkha> tracxn, which I've never heard of, says that was their last one: https://tracxn.com/d/companies/sifive/__AR-ZldFZBmHj7_Xoyqdrnomo71rvsZheUk_7TG_rHpc
<muurkha> so I guess that gave them a year and a half of runway, and they failed to take off
<muurkha> but the USA politician attack on RISC-V was this month
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<suqdiq> sifive said they have money for runways for years and years various times
<suqdiq> maybe ceo was lieing
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<muurkha> if https://morethanmoore.substack.com/p/the-risk-of-risc-v-whats-going-on is correct, I don't know what other explanation there is
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<geist> i get the feeling that that one is a bit overblown
<geist> like the truth is probably not quite as extreme there
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<meowray> does riscv32 support -mcmodel={medlow,medany} ?
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<jrtc27> yes
<jrtc27> it's a bit stupid, in that both can address the whole address space, but it does work
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<meowray> jrtc27: thx. i'm changing -mcmodel= to reject invalid values
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