<sorear>
seems somewhat strange to disable the FPU for the t-head underflow bug when linux's only response to the pentium fdiv bug is to set a flag visible in /proc/cpuinfo
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<mps>
Stat_headcrabed: thanks for info. will test this evening if find time
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<Stat_headcrabed>
mps: I'll send my ddr patch V2, based on this patch, since it's already reviewed
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<mps>
Stat_headcrabed: OK, will add it to test
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<conchuod>
sorear: is there a patch doing that? I'm pretty lost right now cos of being out of office and then my main dev box broke.
<palmer>
conchuod: I'd suggested it. I'd just add a ptrace() flag where userspace can say it wants the broken FPU
<palmer>
not sure if someone else has something
<sorear>
i've seen the suggestion in two or three places but I don't remember if anyone else was suggesting it
<palmer>
sorear: ya, it might have been just me. I wouldn't be super opposed to this defaulting to on, I just tend to stick on the careful side with these things
<palmer>
we'd probably want the same prctl/sysctl stuff we've done for other user-visible things
<sorear>
seems like a ton of complexity that would be nearly impossible to use
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<sorear>
if userspace doesn't use FD it doesn't matter, if userspace does use FD disabling hardware float doesn't actually help unless we're adding a kernel float emulator at the same time
<palmer>
I don't think it's that complicated. We'd already need to check for the errata to inform userspace somehow, and we've already got the dynamic FP enable/disable (for lazy save and such). So at that point it's just defining some errata ctls (which we'll eventually need anyway) and then defining a bit
<xypron>
qemu-system-riscv64 does not trap on jalr x0, a0 with a0 containing an odd address (bit 0 set). It this an implementation bug or does the RISC-V spec require the low bit to be ignored?
<xypron>
Trapping 16bit aligned instruction addresses for rv64,c=false works fine.
<palmer>
xypron: I see "The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to an IALIGN-bit boundary." in a current-ish ISA spec. So it's probably a QEMU bug
<palmer>
oh, maybe I'm wrong -- there's a blurb above it about the least-significant bit
<palmer>
"The target address is obtained by adding the sign-extended 12-bit I-immediate to the register {\em rs1}, then setting the least-significant bit of the result to zero."
<palmer>
so ya, looks like a feature
<xypron>
Thanks
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<Stat_headcrabed>
conchuod: Do we have a way to get time register frequency in userspace?
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