sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<Esmil> conchuod: I talked to Cristian Ciocaltea about upstreaming non-coherent support for the JH7100, but apparently he is on leave
<conchuod> 👍
<conchuod> There's no rush
<Esmil> However yesterday I looked at it again a bit. I have a version that works without DMA_GLOBAL_POOL
<conchuod> Oh cool, how much extra hackery was required?
<Esmil> It's a little more invasive though: http://sprunge.us/KEgMKU
<conchuod> hmm, ill take a look shortly
<Esmil> I should probably just send the JH7100 and cache flushing for the sifive ccache driver though. That is common to both approaches
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<clemens3> loongson is more of a mips architecture.. but just for broader market observation
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<muurkha> clemens3: thanks, super interesting
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<mwette> Has anyone released RISC-V boards with the V extension?
<muurkha> Sipeed?
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<muurkha> 22:32 < mwette> Has anyone released RISC-V boards with the V extension?
<muurkha> 22:35 < muurkha> Sipeed?
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<mwette> muurkha: thanks. I ran a google search "risc-v + sipeed" everything shut down; I then found sipeed on amazon, but no ref to vector extension
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<muurkha> mwette: sipeed has some t-head C910 boards IIRC?
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