sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<geist> ugh, not having zicntr is really lame, it's even mandated by RVA20 and RVA22 (though checking it now, the RVA20U64 and RVA22U64 have slightly different wording re: zicntr)
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<courmisch> geist: why would RDTIME return 0? it's not a security issue like RDCYCLE
<geist> if the firmware or hardware simply doesn't implement it
<geist> then 0 is the only reasonable answer (or an illegal instruction)
<courmisch> unlord: RDTIME can have a rather low frequency, so getting two equal value consecutively is possible
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<courmisch> but they shouldn't be zero (well, except for what geist said)
<geist> well technically they're covered by the Zinctr feature
<geist> and if that's not present, then it can be unimplemented
<geist> i actually checked what linux does, it the riscv vdso does not use it, it always makes a call for gettimeofday
<courmisch> the spec seems to imply that if you have CSR, you have to have TIME, CYCLES and INSTRET?
<geist> that's Zicsr
<courmisch> ah ok, yeah, it's different chapters
<geist> Zinctr is a separate feature bit that says whether or not the counters return
<geist> it was initially i think not separate like that but it got more formalized
<geist> that being said both RVA20 and RVA22 basically mandate it
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