sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<ncopa> does anybody know what kernel driverns are needed for emmc for vision five 2? https://git.aurel32.net/linux.git/log/?h=jh7110-6.5.y
<ncopa> the SD card show up, but not the emmc
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<ncopa> i believe I need to enable something in the kernel but I don't know what
<ncopa> maybe CONFIG_MMC_SPI?
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<bjdooks> are all the mmc busses there? is it detecting a device but not attaching a driver for it?
<mps> ncopa: hm, I now see that I disabled CONFIG_MMC_SPI but can't remember why. could be that enabling it could be fix
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<Esmil> mps: no, MMC_SPI is for talking to MMC using an SPI peripheral (like the unleashed does). the vf2 has dedicated mmc peripherals
<Esmil> ncopa: this tree boots from mmc for me: https://github.com/esmil/linux/tree/jh7110
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<ncopa> Esmil: nice
<ncopa> Esmil: could I have a look at your kernel config?
<ncopa> I'm running kubernetes on visionfive2 :) $ doas k0s kc get pods --namespace=kube-system | tpaste
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<aurel32> ncopa: CONFIG_SPI_CADENCE_QUADSPI
<ncopa> CONFIG_SPI_CADENCE_QUADSPI=y
<ncopa> $ grep CONFIG_SPI_CADENCE_QUADSPI config-starfive.riscv64
<ncopa> seems like it is already enabled
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<ncopa> do I also need CONFIG_MMC_SDHCI? CONFIG_MMC_SDHCI_CADENCE?
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<aurel32> ncpoa: this is the config i am using: https://temp.aurel32.net/config-6.5.0+
<ncopa> thanks
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<Esmil> smaeul: drewfustini: conchuod: No, the JH7100 doesn't work without the DMA_GLOBAL_POOL unfortunately, so chances are that's the same for the rzfive :/
<Esmil> *without CONFIG_DMA_GLOBAL_POOL=y i should say. the pool is still there in the device tree
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<drewfustini> Esmil: bummer, thanks for checking
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<drewfustini> palmer: Esmil: interesting point by icenowy
<drewfustini> Well, considering RZ/Five enables some spec-non-conformant local memory
<drewfustini> (which bypasses MMU) that makes even running generic user space
<drewfustini> doesn't look like a big deal.
<drewfustini> binaries not so viable (PIE ones may still run, but those built to be
<drewfustini> on the default fixed location of binutils will conflict with the MMU-
<drewfustini> bypassing local memory), not supporting it in a multi-platform kernel
<drewfustini> Anyways, I'll post a patch that removes the select of DMA_GLOBAL_POOL and the discussion can move there instead of the TH1520 MMC driver series
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<Esmil> yeah, unfortunately that also means the JH7100 can't be enabled without NONPORTABLE and that and the unmatched are still the two most reliable machines i have :/
<drewfustini> For the distro perspective, do you think RZ/Five could have been supported by a single userspace image? I am uncertain about the issues there.
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<Esmil> i heard someone talk about a really slow workaround by letting opensbi handle faults, but without that it doesn't seem like it
<sorear> does anyone actually have an rz/five to test? the soc documentation is confusing and I'm not confident in any of the interpretations that are floating around
<sorear> contradictory on the extent to which the TCM visibility and address can be configured at runtime
<drewfustini> I was looking last night to see if I could get one but I only saw the official eval board which was about $1,000
<drewfustini> which is beyond my curiosity budget :)
<geertu> sorear: I have an RZ/Five, and got the latest firmware from Prabhakar earlier today.
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<geertu> Until now, my testing was limited (boot modern kernel until unable to mount root, or boot old kernel the board came with)
<geertu> drewfustini: 560.42€ < $1000, AFAIK ;-)
<geertu> OK, still above curiosity budget
<drewfustini> oh, I didn't see that
<drewfustini> yeah :)
<geertu> search RZ/Five at digikey
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<geertu> OMG, Digikey has a picture with the CAN-transceiver mounted ;-)
<drewfustini> geertu: what do you think is a good solution for the DMA_GLOBAL_POOL issue? One hand, I can add a global pool to my th1520 device tree and it works okay with the defconfig. On the other hand, I'm not sure if that is the right decision?
<drewfustini> s/One hand/On one hand/
<geertu> drewfustini: I guess the kernel should be fixed to handle both cases
<geertu> Cfr. what Robin says
<drewfustini> I'm less certain about how that could be done, and ideally I would like to decouple it from my mmc series. I would love to have booting from eMMC on the th1520 in 6.7.
<geertu> Sure
<drewfustini> Palmer suggested I send a patch to remove the DMA_GLOBAL_POOL select.and that could start the thread of discussion
<drewfustini> do you think that is a good idea?
<drewfustini> oh!
<drewfustini> Jisheng is fast :)
<drewfustini> alright, then that serves the purpose of bringing the discussion out of the mmc series and hopefully making sure everyone notices the discussion
<geertu> Depending on non-portable would be fine for now, I guess. And could be final, if it was just for RZ/Five, as it cannot run a standard distro anyway :-(
<geertu> But if you bring JH7100 and Starlight (and what else?) into the picture...
<drewfustini> Esmil: It just effect JH7100, right? JH7110 is okay?
<drewfustini> geertu: " it cannot run a standard distro anyway" thanks for clarifying, i was uncertain about that
<Esmil> drewfustini: yes, for most peripherals, but i'm told some of the graphics may be non-coherent
<geertu> What about ERRATA_THEAD_CMO?
<drewfustini> do you mean as to whether it should be selected?
<drewfustini> ARCH_THEAD selects ERRATA_THEAD_CMO. defconfig has CONFIG_ARCH_THEAD=y. Are you thinking that should change?
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<Esmil> geertu: the ubuntu kernels already enable ERRATA_THEAD_CMO and co-exists with sifive, microchip and JH7110 support just ine
<Esmil> (from the lunar 6.2 kernel onwards that is)
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<courmisch> it must be in the spec somewhere but I can't seem to find it
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<courmisch> when using a vector widening instruction, the CPU must support elements of 2*SEW, I suppose?
<courmisch> so e.g. you can't widen 64-bit elements with just V
<courmisch> oh found it
<courmisch> it's a bit strange. The spec seems to say that Zve64x cannot widen 64-bit elements, but Zve32x can widen 32-bit elements
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