_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sensille> of course the design also works in iverilog, but still not in hardware. i'm out of ideas what to check. tried different power supplies, lowered the clock, tried a different board
<sensille> works in 2 simulators
<sensille> although i can't exactly simulate it due to regular_comb
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