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<riktw>
Hi everyone. I have a quick question. I'm doing stuff with Litex lately, I got a SoC and added a few peripherals and want to make some software for it. My current approach is to use the litex_term to upload new software in it. I compile and then reboot the FPGA, the bios starts and software is loaded in.
<riktw>
This all works pretty nicely. But every boot the bios does a memtest and memory speed test. Is this something that can be disabled easily via an argument on building the SoC, or do I need to comment it out or such in the bios sourcecode?
<_florent_>
this is used here in simulation to avoid corrupting data that has been pre-initialized
<riktw>
@_florent_, Ah cool, I'll give that a try :)
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<sensille>
i really have a hard time with the litex documentation. i have my script that builds the bitstream for ecp5 with diamond. how do i use it for a simulation now? the project is mixed verilog/vhdl
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<gurki>
note that this ^ can backfire badly, since vhdl and verilog are quite different
<sensille>
i tried that some time ago, but the amount of errors it spilled out was not encouraging. trying to get modelsim to work for now.
<gurki>
i wouldnt trust a simulation/validation done with a conversion to be true to the original
<_florent_>
sensille: with modelsim, you'll have to create a small testbench around the generated LiteX design and provide all the files used in the LiteX design to modelsim.
<gurki>
we need vhdlator! :3
<gurki>
scnr
<sensille>
mixelator
<_florent_>
gurki: GHDL has greatly improved the last years on this and we can succesfully already simulate nice VHDL projects with it: Ex Microwatt, NeoRV32 or Mister's Scaler core.
<_florent_>
gurki: I've also used it to develop some VHDL code for clients without issues.
<gurki>
'it runs. somehow.' doesnt equal validation of the original hdl though
<sensille>
the code I use has internal tri-state busses. can ghdl handle that?
<gurki>
i have synthesized both converted and not converted neorv32 for funsies a while ago. quite different results
<gurki>
so no, i dont trust thiw conversion
<gurki>
but im derailing. lets talk sensilles actual problems :)
<jevinskie[m]>
If there’s interest I could resurrect those and add modelsim/questasim support
<gurki>
jevinskie[m]: how can i buy you coffee to convince you to do so? :3
<riktw>
_florent_: I had to go for self.add_constant("CONFIG_MAIN_RAM_INIT") and not SDRAM_TEST_DISABLE as I'm using a Tang nano with hyperram, but that makes development a little easier :)
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<cr1901>
cocotb explicitly doesn't support mingw python (what could they be doing that's _so_ advanced that it _mandates_ MSVC ABI?) and I'm not completely changing my workflow for a single package. So unfortunately I can't use it.
<sensille>
modelsim does not seem to handle the generated verilog well
<sensille>
Iteration limit 5000 reached at time 0 fs.
<sensille>
but i'm still at the start of understanding this
<sensille>
first thing to notice is that it uses non-blocking assignments in always (@*) blocks
<cr1901>
That is considered good form, tho I couldn't tell you why offhand (see Cliff Cummings' papers on nonblocking assignments for an actual reason)
<sensille>
"Guideline: Use blocking assignments in always blocks that are written to generate
<sensille>
combinational logic"
<sensille>
(from the mentioned paper, which states the opposite)
<cr1901>
sensille: You're correct, I swapped the two in my head
<cr1901>
meaning if I wrote out an example I would've used "=" and called in "nonblocking" lmao
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