07:28 <riktw> Hi everyone. I have a quick question. I'm doing stuff with Litex lately, I got a SoC and added a few peripherals and want to make some software for it. My current approach is to use the litex_term to upload new software in it. I compile and then reboot the FPGA, the bios starts and software is loaded in.

07:29 <riktw> This all works pretty nicely. But every boot the bios does a memtest and memory speed test. Is this something that can be disabled easily via an argument on building the SoC, or do I need to comment it out or such in the bios sourcecode?

08:11 <_florent_> riktw: Hi, you can disable the sdram test with https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L219

08:12 <_florent_> this is used here in simulation to avoid corrupting data that has been pre-initialized

08:16 <riktw> @_florent_, Ah cool, I'll give that a try :)

11:41 <sensille> i really have a hard time with the litex documentation. i have my script that builds the bitstream for ecp5 with diamond. how do i use it for a simulation now? the project is mixed verilog/vhdl

16:04 <_florent_> sensille: If you want to simulate with verilator, you'll first have to convert your vhdl to verilog, this can be done like this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/neorv32/core.py#L121-L171

16:06 <gurki> note that this ^ can backfire badly, since vhdl and verilog are quite different

16:06 <sensille> i tried that some time ago, but the amount of errors it spilled out was not encouraging. trying to get modelsim to work for now.

16:07 <gurki> i wouldnt trust a simulation/validation done with a conversion to be true to the original

16:08 <_florent_> sensille: with modelsim, you'll have to create a small testbench around the generated LiteX design and provide all the files used in the LiteX design to modelsim.

16:09 <gurki> we need vhdlator! :3

16:09 <gurki> scnr

16:09 <sensille> mixelator

16:10 <_florent_> gurki: GHDL has greatly improved the last years on this and we can succesfully already simulate nice VHDL projects with it: Ex Microwatt, NeoRV32 or Mister's Scaler core.

16:10 <_florent_> gurki: I've also used it to develop some VHDL code for clients without issues.

16:11 <gurki> 'it runs. somehow.' doesnt equal validation of the original hdl though

16:11 <sensille> the code I use has internal tri-state busses. can ghdl handle that?

16:12 <gurki> i have synthesized both converted and not converted neorv32 for funsies a while ago. quite different results

16:13 <gurki> so no, i dont trust thiw conversion

16:14 <gurki> but im derailing. lets talk sensilles actual problems :)

17:39 <jevinskie[m]> I once added cocotb support which worked, iirc, with modelsim. I also once made a VPI wrapper around the LiteX verilator sim modules so they could work across simulators (iverilog was my target then) https://github.com/jevinskie/litex/blob/jev/main-old/litex/build/sim/cocotb.py

17:40 <jevinskie[m]> If there’s interest I could resurrect those and add modelsim/questasim support 

17:46 <gurki> jevinskie[m]: how can i buy you coffee to convince you to do so? :3

17:57 <riktw> _florent_: I had to go for self.add_constant("CONFIG_MAIN_RAM_INIT") and not SDRAM_TEST_DISABLE as I'm using a Tang nano with hyperram, but that makes development a little easier :)

19:49 <cr1901> cocotb explicitly doesn't support mingw python (what could they be doing that's _so_ advanced that it _mandates_ MSVC ABI?) and I'm not completely changing my workflow for a single package. So unfortunately I can't use it.

20:16 <sensille> modelsim does not seem to handle the generated verilog well

20:16 <sensille> Iteration limit 5000 reached at time 0 fs.

20:16 <sensille> but i'm still at the start of understanding this

20:18 <sensille> first thing to notice is that it uses non-blocking assignments in always (@*) blocks

20:19 <cr1901> That is considered good form, tho I couldn't tell you why offhand (see Cliff Cummings' papers on nonblocking assignments for an actual reason)

20:19 <sensille> "Guideline: Use blocking assignments in always blocks that are written to generate

20:19 <sensille> combinational logic"

20:24 <sensille> (from the mentioned paper, which states the opposite)

20:26 <cr1901> sensille: You're correct, I swapped the two in my head

20:26 <cr1901> meaning if I wrote out an example I would've used "=" and called in "nonblocking" lmao

23:53 <jevinskie[m]> There is a toggle in the Verilog generator that might fix that  https://github.com/enjoy-digital/litex/blob/3a2586c48b276b66b7d92037c12c0d9e2aff8836/litex/gen/fhdl/verilog.py#L534