_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
so-offish has quit [Ping timeout: 264 seconds]
GNUmoon has quit [Ping timeout: 240 seconds]
GNUmoon has joined #litex
Degi has quit [Ping timeout: 245 seconds]
Degi has joined #litex
GNUmoon has quit [Remote host closed the connection]
GNUmoon has joined #litex
<sensille> zyp: how do you mean? cpu time in the communcation functions?
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
<zyp> sensille, yes
<sensille> no idea, can't be much. just building/parsing a smallish udp packet
<sensille> one per millisecond
<zyp> I looked at both litehm2, litex-cnc and colorcnc (I think it was called), but neither was entirely what I wanted, so I started my own approach based on a custom ethercat-like protocol where a single packet passes through a chain of devices that rewrites it
<zyp> because part of what I want to do is distribute IO across multiple boards: https://bin.jvnv.net/file/sOo86.mp4
<sensille> my approach was to built on the 20+ years maturity of the existing code, host+fpga side
<zyp> yeah, I get that, it just doesn't suit what I want to do well :)
<zyp> but I'm curious how the communication performance I'm getting compares to other ethernet-based devices
<sensille> i found ethercat quite appealing, but was repelled by the patents on it
<zyp> indeed, that's why I'm not attempting to implement actual ethercat
<sensille> but nice work if you can already pass packets through both ports
<zyp> my main goal is to make something to drive this thing: https://bin.jvnv.net/file/2pVce.jpg
<zyp> by making a custom fpga-based controller card that hooks up to the original power electronics
<zyp> so I'm making custom hardware, which means I want the flexibility to handle arbitrary ADCs and similar in gateware, so the hm2 approach seems a little constraining
<zyp> wheras colorcnc/litex-cnc is apparently based on etherbone, which seems like it'll be a performance bottleneck if you've got many signals
<_florent_> zyp: interesting project! Feel free to share advance/progress here, I'm also interested by this :)
<_florent_> zyp: Etherbone is indeed probably not the best for your application, it's mostly intended for MMAP.
<zyp> I've designed it so the devices contains metadata about what signals it got, which types they have and at what offset in the data frame they're located, so I can simply just declare a few signals like this: https://paste.jvnv.net/view/Gy09s and have them show up in linuxcnc: https://bin.jvnv.net/file/WYbrd.png
<tpb> Title: JVnV Pastebin – View paste – Untitled (at paste.jvnv.net)
<_florent_> zyp: If you want similar latency than Ethercat, you'll indeed have to have a non-standard MAC.
<_florent_> zyp: Another possibility if you want to reuse LiteEth could be to have a custom protocol over UDP, ex here with just raw streaming:
<zyp> yeah, right now I'm using the standard mac, with a custom L3 handler, so each device adds latency corresponding to the preamble and L2 header, plus CDC
<zyp> so probably on the order of a hundred ns per device
<zyp> but that drowns in the host side latency, linuxcnc says my data exchange function takes 40-50 us to execute
Guest93 has joined #litex
Guest93 has quit [Client Quit]
FabM has quit [Quit: Leaving]
so-offish has joined #litex
so-offishul has joined #litex
so-offish has quit [Ping timeout: 246 seconds]
<cr1901> _florent_: Did you get a chance to confirm the bug? If not, should I open an issue anyway?
<cr1901> bisecting could potentially, be difficult, but I'll try
<sensille> zyp: do you write your own linuxcnc drivers, or intend to do so?
so-offishul has quit [Quit: Leaving]
<zyp> sensille, yes, I did
<sensille> from scratch or by starting from the existing mess?
<zyp> I was looking at a few existing drivers for inspiration, but wrote it from scratch
<sensille> that is quite the feat :)
<zyp> I think I took a fairly unconventional approach: https://paste.jvnv.net/view/xgWVd :)
<tpb> Title: JVnV Pastebin – View paste – Untitled (at paste.jvnv.net)
<sensille> still trying to port to colorlight ... etherbone just works, but the cpu doesn't seem to run
<_florent_> cr1901: sorry, haven't had time yet, you can open an issue
so-offish has joined #litex
<zyp> sensille, what type of uart are you using for the bios console? have you checked it's not just waiting for uart flow control?
<zyp> a regular hardware uart will output bytes regardless of whether anybody are listening or not, but e.g. the crossover uart will block until it's polled
cr1901 has quit [Read error: Connection reset by peer]
cr1901 has joined #litex
<cr1901> _florent_: Ack, will do when I get the chance
dark_star_1 has quit [Ping timeout: 245 seconds]
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
<_florent_> sensille: with the crossover uart, you can use this to avoid it being blocked at startup: https://github.com/360nosc0pe/scope/blob/main/sds1104xe.py#L134
key2 has joined #litex
<sensille> nice. i don't use a bios, though. just a short loop that is supposed to blink the led. i guess i need to learn to simulate with litex. for some miracle that wasn't necessary yet
dark_star_1 has joined #litex